Memory Map

giorgos tsoumplekas

Dear all,

We are working on C6654 platform. We create a memory map for C6654 platform , but the last 128 KB are not currently used (we planned to use them as cache).

In cfg file we have define the cache module.

When the program runs we notice that this unused region (128 kb) is accessed . The most often value that we see is the oxBEBEBE , that is the value for stack initialization.

When we changed the memory map an we used all the L2 memory , the values that are keep in the latest 128 KB are not changed.

The half higher address is used for the code and it is logical to not change when the program is executed.

Why does the content of the latest 128 KB of address are changed when we have not configured all the L2 RAM. Probably there is not memory leak because this phenomenon disappeared when we use all the L2 memory. Is any MPU to avoid access this region of memory?

Best regards

George

over 8 years ago

0 Sasha Slijepcevic over 8 years ago

TI__Mastermind 37985 points

George,
can you post linker command files and the resulting memory maps for those two use cases? Is the unused memory region initialized for stack before or after BIOS_start? If there are dynamic tasks created, try looking at that memory before and after Task_create.

0 giorgos tsoumplekas over 8 years ago in reply to Sasha Slijepcevic

Expert 1840 points

Good morning,

Please find the two different post. I use dynamic task but thei stacks have been allocated in DDR3.

The Swi and Hwi stacks are strored in L2.5008.UsageallL2.rar 4075.UsagePartOfL2_128LastBytesNotUsed.rar.

Best regards

George

0 Sasha Slijepcevic over 8 years ago in reply to giorgos tsoumplekas

TI__Mastermind 37985 points

Both linker command files you sent me are using approximately the same amount of L2 memory (there is 2 bytes difference):
IDRAM0 (RWX) : org = 0x800000, len = 0x95000
IPRAM (RWX) : org = 0x895000, len = 0x6afff
and
IDRAM0 (RWX) : org = 0x800000, len = 0x95000
IPRAM (RWX) : org = 0x895000, len = 0x6affc
This means you are allowing the linker to use all that memory as needed. How do you allocate 128K for cache?

0 giorgos tsoumplekas over 8 years ago in reply to Sasha Slijepcevic

Expert 1840 points

Hello,
You are right
Although I have defined only a part of L2 section in memory map of platform , the linker cmd that is generated includes the whole L2 memory.
I define the cache using the CCS6 gui wizard under Tools->RTSC->Platform ->New .In the current configuration the cache is 0 Bytes

Best regards
George

0 Sasha Slijepcevic over 8 years ago in reply to giorgos tsoumplekas

TI__Mastermind 37985 points

George,
to find out why the linker command file is the same even though you are changing the memory map settings in the platform file I would have to see the configure command line from your console output and the content of your platform package.
I know that we had some cache configuration problems in earlier versions of XDCtools and SYS/BIOS. I don't know which version are you using, so that could be a problem.

Also, in both cases the linker had the last 128KB of L2 (the memory range 0x8e0000-0x8fffff) available, but it didn't allocate anything there. If you configured L2 cache to be 128KB, you would be potentially overwriting allocated memory with cache but you just got lucky that the linker did not use that memory. If that memory is used for cache anything could be written there.

0 giorgos tsoumplekas over 8 years ago in reply to Sasha Slijepcevic

Expert 1840 points

Hello,
We are using the xdctools_3_30_01_25_core. If I set the remaining memory (128 KB) temporarily as a Read only region, can avoid any access in this region of memory.
Best regards
George

0 Sasha Slijepcevic over 8 years ago in reply to giorgos tsoumplekas

TI__Mastermind 37985 points

As far as I know, that version of XDCtools does not have any cache related bugs. You most likely still have a problem, but without seeing more of your files I can't really help much.

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