2.4.3 in spru862b mentions that:
An L2 cache line is 128 bytes. The cache controller operates on all lines that are “touched” by the
specified range of addresses. Note that the maximum byte count that can be specified is 4 × 65 535 bytes
(on some C64x+ devices the maximum is 4 × 65 408 bytes, see your device-specific data manual), that is,
one L2 cache operation can operate on at most 256K bytes. If the external memory buffer to be operated
on is larger, multiple cache operations have to be issued.
And Advisory 1.6 of DM3730 Errata (sprz319f) tightened this limitation to:
When performing any block cache operation, such as "Writeback", "Writeback with
Invalidate", or "Invalidate", for any memory controller or memory range (e.g., L1P, L2,
L1D) the word count programmed must be less than or equal to 0xFF80. If a value
greater than 0xFF80 is desired, then this must be broken into multiple operations. The
following registers are affected: L2WWC, L2WIWC, L2IWC, L1PIWC, L1DWIWC,
L1DWWC, and L1DIWC.
I'm using DSP/BIOS 5.41 on a DM3730 device.
When I use "BCACHE_inv" and friends, do I need to take care of this limitation myself, or is it handle autimatically in the function?
