Load balancing in TI RTOS for A15 multicore pack

Hi Mahantesh,

Yes, TI-RTOS has multi-core support if you use it in SMP mode.

I discussed your questions with our kernel experts. Please find the answers from our kernel expert in-lined and the following are the documents for SMP. Note SYS/BIOS is the name formerly used for TI-RTOS Kernel.

Mahantesh Kothiwale said:

1) TI-RTOS, on A15 multicore (In a TCI6638K2K SoC) can do the dynamic load balancing of tasks across ARM cores ?

[ Kernel Expert – yes.  If using SMP mode. ]

Mahantesh Kothiwale said:

If yes,

- what criteria applied for load balancing..? (Ex: percentage of CPU load)

[ Kernel Expert – see the doc links above.  SYS/BIOS scheduler is event driven and not time-sliced or “fairness” based.  The highest priority thread (or threads in SMP case) that are ready to run will run. ]

Mahantesh Kothiwale said:

- Do TI RTOS use the ARM IPIs for waking up TASKs on another core in runtime..?

[ Kernel Expert – I don’t know what IPIs are.  SMP/BIOS uses inter-core interrupt line to trigger the other core as necessary for scheduler events. ]

Mahantesh Kothiwale said:

- If I don't want to do runtime load balancing, is it possible to statically assign TASKs to fixed cores ?

 [ Kernel Expert – Yes.  There’s a new ‘affinity’ parameter in the Task_Params structure. You can lock a task to a given core using this field. ]

Mahantesh Kothiwale said:

2) In a design, 2 TCI6638K2K SoCs are being connected Via Hyperlink.. In this case, Can I run the set of TASKs, across 2 SoCs, under single RTOS image..? I mean can it work like a conventional Octa core processor..? How the dynamic load balancing and waking up a TASK on core of one SoC from core of another SoC ?

[ Kernel Expert – No. SMP/BIOS only works within the cores on a given device. No support for multiple devices. ] 

Mahantesh Kothiwale said:

3) Did anyone use TI-RTOS on TCI6638K2K ?

[ Kernel Expert – question for someone in the community to answer. But, we have many customers using TI-RTOS on TCI6638K2K. It is part of the multicore SDK. ]

Vikram

Hi Mahantesh,

Mahantesh Kothiwale said:

1) In TCI6638K2K, Can this TI SMP RTOS, is meant to run only on ARM Corepac ..?


Can DSP corepac run this SMP RTOS ..?
If no, what is the RTOS execution model on Corepac..? Need to make the independent images of SYS/BIOS run on individual DSP cores..? 

Presently, we support SMP mode of operation only on the multi-core Cortex-A15s and dual-core Cortex-M3/M4s. We do not support running in SMP mode on the DSPs. On the DSPs, the TI-RTOS kernel can be run in AMP mode i.e. each DSP core runs its own instance of the TI-RTOS kernel.

Mahantesh Kothiwale said:

2) Also, I am trying to understand from Hyperlink document, how a line of code running on ARM core or DSP core can access the I/O peripheral (Memory mapped registers) on another SoC via Hyperlink..?

Can the 40-bit address space be divided into two parts ..? (One part for each SoC)..

Do TeraNet bus decode some MSBs of 40 bit address to pass the transaction over Hyperlink ..?

Can you please point me to the right document explaining the address mapping across 2 SoCs connected over Hyperlink ..?
Also, the CCS tool-chain support to define 64 bit pointers to hold 40 bit addresses and necessary linker scripting to locate the particular data and code segments to the addresses mapped to SoC1 and SoC2.

Hyperlink related questions would be better answered on the Keystone 2 device forum. Can you try posting your Hyperlink question on that forum ?

Best,
Ashish