Hello everybody,
I have a question concerning interrupt handling using TI-RTOS version 2.12.1.33 on a TMS320F2837xD processor. We registered a set of interrupts with the effect that some previously enabled interrupts were disabled afterwards.
We configured four interrupts using Hwi_create and afterwards using Hwi_enableInterrupt to enable the interrupt. Precisely we registered XINT2 (1,5), IPC1 (1,14), XINT1 (1,4), IPC0 (1,13) in the described order, which lead to a behavior that is still inexplicable to us. The result was that IPC1 was not enabled after the registration process.
What we discovered is that calling Hwi_create for XINT1 disabled the previously enabled IPC1 interrupt. More generally a call of Hwi_create disabled every previously enabled interrupt with a y-index greater than 8 (on the right side of the PIE Channel Mapping table).
A look in the debugger lead us to the following line of code in the Hwi_disablePIEIER function of the HWI.c file, were a set of PIEIERx.y bits is cleared.
*((UInt16 *)PIECTRL_ADDR + (groupNum * 2)) &= (~pieMask & 0xff);
What surprised us is that due to the AND-operation of the 16-bit pie mask with 0xff every interrupt with y greater than 8 is disabled anyway (no matter what value pieMask holds).
Could this possibly be a bug or did we simply forget some important configuration? Maybe a preprocessor definition for a special processor family or similar?
As an additional information Hwi_create was called with:
Hwi_Params p;
Hwi_Params_init(&p);
p.enableAck = true;
p.enableInt = false;
The disableMask is set to its default value MaskingOption_SELF.
Kind regards,
Tobias
