Hello I am trying to run the PWM modules in the OMAP 138 LCDK. Given that module zero is connected to the Ethernet PHY, I decided to use module 1.
I am trying to implement the example waveform in the OMAP-L138 user guide on page 472 figure 17-25. For which the register initialization is given on Table 17-19. I am not interested in interrupts, just a simple waveform generation. So I am setting PLL, Setting the Pins, and the Initializing the resisters as shown in the Table 17-19, yet I don;t see any signal out in the pins using oscilloscope, either open or with a resistor to gnd of 10 Kohms.
The following shows essentially what I am doing. Is there anything I am missing?. I am expecting after I do this the PWM modules should generate my signals... thank you.
I include:
#include <ti/csl/soc_C6748.h>
#include <ti/csl/cslr_syscfg0_C6748.h>
#include <ti/csl/cslr_psc_C6748.h>
#include <ti/csl/cslr_pllc_C6748.h>
#include <ti/csl/cslr_ehrpwm.h>
PLL section:
CSL_PllcRegsOvly pllcRegs = ((CSL_PllcRegsOvly) CSL_PLLC_0_REGS);
/* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR */
CSL_FINST(pllcRegs->PLLCTL, PLLC_PLLCTL_PLLENSRC, CLEAR);
/*Set PLL BYPASS MODE */
CSL_FINST(pllcRegs->PLLCTL, PLLC_PLLCTL_PLLEN, BYPASS);
/*wait for some cycles to allow PLLEN mux switches properly to bypass clock*/
delay(150);
/* Reset the PLL */
CSL_FINST(pllcRegs->PLLCTL, PLLC_PLLCTL_PLLRST, ASSERT);
/*PLL stabilisation time*/
delay(1500);
/*Program PREDIV Reg, POSTDIV register and OSCDIV1 Reg
1.predvien_pi is set to '1'
2.prediv_ratio_lock_pi is set to '1', RATIO field of PREDIV is locked
3.Set the PLLM Register
4.Dont program POSTDIV Register
*/
/* Set PLL Multiplier */
pllcRegs->PLLM = pll_multiplier;
/*wait for PLL to Reset properly=>PLL reset Time*/
delay(128);
/*Bring PLL out of Reset*/
CSL_FINST(pllcRegs->PLLCTL, PLLC_PLLCTL_PLLRST, DEASSERT);
/*Wait for PLL to LOCK atleast 2000 MXI clock or Reference clock cycles*/
delay(2000);
/*Enable the PLL Bit of PLLCTL*/
CSL_FINST(pllcRegs->PLLCTL, PLLC_PLLCTL_PLLEN, PLL);
delay(2000);
Pin Mux:
// Key to be written to enable the pin mux registers for write
sysRegs->KICK0R = 0x83E70B13;
sysRegs->KICK1R = 0x95A4F1E0;
//Enable the pinMux for eHRPWM EPWM1_A and EPWM1_B
sysRegs->PINMUX5 |= ((CSL_SYSCFG_PINMUX5_PINMUX5_3_0_EPWM1A)<<(CSL_SYSCFG_PINMUX5_PINMUX5_3_0_SHIFT))\
|((CSL_SYSCFG_PINMUX5_PINMUX5_7_4_EPWM1B)<<(CSL_SYSCFG_PINMUX5_PINMUX5_7_4_SHIFT));
PWM Init:
//eHRPWM register overlay
CSL_EhrpwmRegsOvly pwm1Regs = (CSL_EhrpwmRegsOvly)(CSL_EHRPWM_1_REGS);
// Enable Power to eHRPWM ------------------------------------------------------
// Set NEXT state of eHRPWM to ENABLE
psc1Regs->MDCTL[CSL_PSC_EHRPWM] = CSL_PSC_MDCTL_NEXT_ENABLE;
// move eHRPWM PSC to Next state
psc1Regs->PTCMD = CSL_PSC_PTCMD_GO0_SET;
// wait for transition
while ( CSL_FEXT(psc1Regs->MDSTAT[CSL_PSC_EHRPWM], PSC_MDSTAT_STATE)
!= CSL_PSC_MDSTAT_STATE_ENABLE);
pwm1Regs->TBPRD=0x0258;
pwm1Regs->TBPHS=((CSL_EHRPWM_TBPHS_TBPHS_RESETVAL)<<(CSL_EHRPWM_TBPHS_TBPHS_SHIFT));
pwm1Regs->TBCTR=0x0000;
pwm1Regs->TBCTL=((CSL_EHRPWM_TBCTL_CTRMODE_UPDOWN)<<(CSL_EHRPWM_TBCTL_CTRMODE_SHIFT))
| ((CSL_EHRPWM_TBCTL_PHSEN_DISABLE)<<(CSL_EHRPWM_TBCTL_PHSEN_SHIFT))
| ((CSL_EHRPWM_TBCTL_PRDLD_FROMSHADOW)<<(CSL_EHRPWM_TBCTL_PRDLD_SHIFT))
| ((CSL_EHRPWM_TBCTL_SYNCOSEL_DISABLE)<<(CSL_EHRPWM_TBCTL_SYNCOSEL_SHIFT))
| ((CSL_EHRPWM_TBCTL_HSPCLKDIV_DIVBY4)<<(CSL_EHRPWM_TBCTL_HSPCLKDIV_SHIFT))
| ((CSL_EHRPWM_TBCTL_CLKDIV_DIVBY128)<<(CSL_EHRPWM_TBCTL_CLKDIV_SHIFT));
pwm1Regs->CMPA= 0x0190;
pwm1Regs->CMPB= 0x01F4;
pwm1Regs->CMPCTL=((CSL_EHRPWM_CMPCTL_SHDWAMODE_SHADOW)<<(CSL_EHRPWM_CMPCTL_SHDWAMODE_SHIFT))
| ((CSL_EHRPWM_CMPCTL_SHDWBMODE_SHADOW)<<(CSL_EHRPWM_CMPCTL_SHDWBMODE_SHIFT))
| ((CSL_EHRPWM_CMPCTL_LOADAMODE_TBCTRZERO)<<(CSL_EHRPWM_CMPCTL_LOADAMODE_SHIFT))
| ((CSL_EHRPWM_CMPCTL_LOADBMODE_TBCTRZERO)<<(CSL_EHRPWM_CMPCTL_LOADBMODE_SHIFT));
pwm1Regs->AQCTLA=((CSL_EHRPWM_AQCTLA_CAU_EPWMXAHIGH)<<(CSL_EHRPWM_AQCTLA_CAU_SHIFT))
| ((CSL_EHRPWM_AQCTLA_CAD_EPWMXALOW)<<(CSL_EHRPWM_AQCTLA_CAD_SHIFT));
pwm1Regs->AQCTLB=((CSL_EHRPWM_AQCTLB_CBU_EPWMXBHIGH)<<(CSL_EHRPWM_AQCTLB_CBU_SHIFT))
| ((CSL_EHRPWM_AQCTLB_CBD_EPWMXBLOW)<<(CSL_EHRPWM_AQCTLB_CBD_SHIFT));
