Questions on RTSC platform for C66 core on AM572x

Hi,

I consulted an expert on your question and got the following:

Answer to Question2:

The reference platform uses the CPU frequency that was being programmed by the GEL files on the EVM. The customer is expected to change the frequency value to match the frequency they are programming the DSP clock to run at. Please note that SYS/BIOS does not program the DSP clock PLL. The platform CPU frequency is a way to tell SYS/BIOS what frequency the CPU is actually running at.

Answer to Question3:

That is correct. If cache size is set to the max of 256KB, remaining 32KB is statically mapped as SRAM and available for use by application.

Best regards,

Murat

Hi Murat,

Thank you for prompt response. There is one last piece of information that is still missing:

What is the start address of the 32K SRAM? Is it at the end of the L2 region? If, for example, I decide to configure 128K as cache and the rest as SRAM, I am going to have 128K+32K=160K SRAM. What will be the starting address of this 160K block? Will it be contiguous (hopefully) or I will get 128K and 32K as two blocks separated by the cache area?

thanks

Michael

Murat, any update on this?

thanks

Michael

I will check with the team and get back soon.

Sorry Michael,

I will try to get back on Friday.
Murat

Hi Michael,

The address ranges for the L1DSRAM, L1PSRAM and L2SRAM can be found in the TRM.

Lets take the L2 SRAM for example. It is 288KB on AM572X. If say Cache size is configured to be 128KB then the first 160KB (288KB - 128KB) of L2SRAM memory region is configured as SRAM and the remaining 128KB is Cache. Same concept applies to L1D and L1P memory.

Best,

Ashish

Hi Ashish,

Thanks for clarification. I am curious about the 32KB that are always SRAM. Is this limitation driven by HW or by SW (SYSBIOS) resource utilization?

The reason I am asking is if this is a HW limitation one should expect to see this 32KB region to be present in the TRM in DSP memory map. If it is a SW limitation then a note explaining it would be useful too.

thanks again,

Michael

Ashish,

Is there a section within the TRM AM572x/1x parts (SRPUHZ6F or SPRUHZ7C) that explicitly states this memory layout with regard to partitioning between SRAM and CACHE ?

The closest I can find within the TRM's are sections...

1.3.2 DSP Subsystems

5.1.1 DSP Subsystems Key Features (TMS320C66x DSP CorePac memory components)

I wasn't able to get a clear answer from the TRM (nor other referenced corepac documents) regarding where the 32 KiB (always SRAM non-Cacheable portion) memory was located, i.e. it it located at the base of DSP_L2 or at the upper end.

It would be nice if this detail was clearly stated somewhere in the documentation similar to previous TI devices such as the SPRS814A (TMS320C6655/57) section 5.1.3.

It might be stated somewhere within the TRM's ~8000 pages (SPRUHZ6F or SPRUHZ7C), but I haven't been able to find it.

Thanks,

-George

Hi Michael,

Michael Shklyarman said:

I am curious about the 32KB that are always SRAM. Is this limitation driven by HW or by SW (SYSBIOS) resource utilization?

The 32KB of L2 SRAM that always behaves like SRAM is a HW feature.

Best,
Ashish

Hi George,

George Lathrop said:

Is there a section within the TRM AM572x/1x parts (SRPUHZ6F or SPRUHZ7C) that explicitly states this memory layout with regard to partitioning between SRAM and CACHE ?

I have submitted documentation feedback requesting TRM to specify the mapping of the 32KB region

regards,

Michael