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Using the Timers of a omapl137 with sysbios on the dsp

Other Parts Discussed in Thread: SYSBIOS

Hi

I have been trying to use the timers of the omapl137 in sysbios without luck. I started two thread (one for basic questions and one to troubleshoot an exception) both suggested to move the question to the TI-RTOS forum.

I have the rCSL code using the timers working. This example comes with the rCSL package and is was very simple to compile and test. I'm now trying to run the same example, of course with the modification I know need to happen, to sysbios.

I start with the SYSBIOS, typical project for the DSP side of the omapl137. So far so go, code compiles and prints the System_printf messages. I have also halted the code and check with timer is SYSBIOS using for the clock and timer module:

  

Question #1: the omap has 2 64 bit timers that can be used as 4 32 unchained. Can I assume that timerid0 corresponds to #define CSL_TMR_0_REGS                     (0x01C20000u)?

Question #2: I think sysbios uses the timers in 32 bit unchained? which of the 2 32 bit is it timerid0? The clock module only allows you to pick timerid0-7 and I have seen in other modules the concept of upper and lower half. As I only have a clock module enable and not the timers I'm not really sure which of the 32 bits I'm using.

I then enable the timers module, add some code to check the number of timers and their status and print the following:

timer_number: 0 INUSE
timer_number: 1 FREE
timer_number: 2 INUSE
timer_number: 3 INUSE

Question #3: is it maybe that timer 0,1,2,3 correspond to timer 0 12, timer 0 34, timer 1 12, timer 1 34? They are reference in the rCSL as:

// Reset the Counter for Timer0

CSL_FINST(tmr0Regs->TIM12, TMR_TIM12_TIM12, RESETVAL);
CSL_FINST(tmr0Regs->TIM34, TMR_TIM34_TIM34, RESETVAL);

tmr0Regs -> 0x01C20000u

I need to use a timer but it needs to be the TIM12 from the omapl137 technical reference, since it is the only side that has the CMP (compare registers)

Question #4: Is it possible to configure the compare registers from sysbios?

Question #5: is it ok to use the following declaration for a function "interrupt void TIMER0_34_isr (void)" in sysbios?

  • Hi Haffiz,

    Hoffiz said:

    Question #1: the omap has 2 64 bit timers that can be used as 4 32 unchained. Can I assume that timerid0 corresponds to #define CSL_TMR_0_REGS                     (0x01C20000u)?

    You can look at the "Device" tab in "Timer" module's ROV view. It shows the timer device base address.

    Hoffiz said:

    Question #2: I think sysbios uses the timers in 32 bit unchained? which of the 2 32 bit is it timerid0? The clock module only allows you to pick timerid0-7 and I have seen in other modules the concept of upper and lower half. As I only have a clock module enable and not the timers I'm not really sure which of the 32 bits I'm using.

    Yes, by default SYS/BIOS will configure the timers to run in unchained mode. The mode can be changed by modifying Timer.timerSettings[] global config param (see Timer64 cdoc for more info and example code) in your application's cfg file. I would suggest manually editing the cfg file instead of trying to do it via XGCONF (GUI config tool).

    All even timer Ids correspond to first half of timer and odd timer Ids correspond to second half. So TimerId0 corresponds to first half of Timer0.

    Hoffiz said:

    Question #4: Is it possible to configure the compare registers from sysbios?

    I am not aware of any compare registers in Timer64. Can you elaborate more ?

    Hoffiz said:

    Question #5: is it ok to use the following declaration for a function "interrupt void TIMER0_34_isr (void)" in sysbios?

    Answer is no. The timer function you pass to the Timer_create() function is a regular function. SYS/BIOS has an interrupt dispatcher that handles all the saving of context that an ISR is required to do.

    Best,

    Ashish

  • Thank you very much your reply is very helpful.

    I've created a project to control the timers and I'm able to control the timers from sysbios. All timers but timer number 0, which makes sense this is the clock module timer:

    enter main()
    enter taskFxn()
    timer_number: 0 INUSE
    timer_number: 1 FREE
    timer_number: 2 INUSE
    timer_number: 3 INUSE
    timer012cnt: 10000
    timer034cnt: 40
    timer112cnt: 20
    timer134cnt: 10
    timer112cmp0cnt: 20
    exit taskFxn()

    Timer number 0 reaches 10k as I have a Task_sleep(10000) after enabling the timers.

    I think most of my problems were due to the incorrect function declaration and not knowing which timerid correspond to which physical timer.

    Compare register: each timer has a compare register for one of the halves of the timer, I'm assuming the lower half, it adds the functionality to trigger DMA and interrupts once the count reaches a compare register. For example, if the timer is set to 100 counts, a compare register can be set at 50 and trigger an event,.... on top of the timer interrupt at 100. I've been referencing: SPRUH92D–March 2013 page 1278, very useful feature.