RTOS/TMS320C6745: C6745 HWI

Kz777 said:

But, when we look another HWI category in the .tcf file, system automatically assign,

HWI_IN11(_HSRTDX_xmt),HWI_12(_HSRTDX_rec),HWI_RESERVED1,HWI_INT14(CLK_F_isr).

We tried to disable these interrupt , there is not able to choice disble.

Do you know how to disable HWI for reserved interrupt on .tcf file ?

Have you enabled RTDX?

If so, it might be forcing HWI_INT11 and HWI_INT12 to be used.

Regards,

- Rob

Hi Rob,

Thanks. First of all , I 'll try to mask another HWI on INT4 using bellow API.

bios.HWI_INT4.interruptBitMask

If we still have issue, I will back to you again.

Regards,

Kz777

Hi Rob,

I am so sorry for my late input.

Actually, this issue was fixed when we set to bellow

bios.HWI_INT4.interruptMask = "all";

but, when I checked it deeply, this issue due to some INT14 nest during INT4 processing.

when I check HWI_INT14(CLK_F_isr), this INT control bios timer.

Is it able to disable this INT14 nest during INT 4 processing ?

Does it affect any system clock delay ?

Regards,

Kaz

Hi Rob,

Thanks for your input . Sorry I miss input command. Your point is collect. I have just do your instractuion way.

Also, I test 0x4000 bit mask method.

We have just concerned INT14 mask affect to system. I will discuss it customer based on your comment.

Regards,

kz777

Hi Rob,
Sorry, I would like to ask again regarding INT14 (BIOS Timer) more detail.
This Int14 correct name is HWI_INT14(CLK_F_isr). According to your estimation , this timer delay should be during masking. After that, it will catch up to the total system. So, I would like to know more information this CLK_F_isr detail. do you have any document for this ?
Regards,
Kz777

Kz777 said:

So, I would like to know more information this CLK_F_isr detail. do you have any document for this ?

No, there is no architecture document for CLK_F_isr.

CLK_F_isr is, as you've seen, the ISR for the CLK module's periodic timer interrupt.  It's main job is to increment the CLK_R_time variable, which is the CLK module's 'tick' time.  It runs without enabling interrupts.

After incrementing the CLK_R_time variable, it calls the HWI dispatcher, which runs a function that services CLK objects.  One of these objects is a KNL object that allows keeping track of KNL ticks and running timeout-based processing (such as waking up a TSK that has an expired timeout with SEM_pend()).  Since the HWI dispatcher is called, interrupts are enabled for running the function configured into that HWI vector.

If interrupts are disabled for longer than the CLK tick period (which is typically 1 ms) then a CLK tick can be missed, thereby skewing the wallclock timebase kept by CLK.  But if your application is disabling interrupts for > 1 ms, then it's most likely going to suffer more than just missed CLK interrupts.

Regards,

- Rob

Hi Rob,

Thanks for your input. I would like to one confirmation regarding bellow,

>If interrupts are disabled for longer than the CLK tick period (which is typically 1 ms) then a CLK tick can be missed, thereby skewing the >wallclock timebase kept by CLK.  But if your application is disabling interrupts for > 1 ms, then it's most likely going to suffer more than just >missed CLK interrupts.

-our application use case , Int4 GPIO HWI is setting per 20 usec. If  we mask INT14(CLK_F_isr), during each of 20usec term will be disabled.

Your mentioned 1msec tick period mean, this each of 20usec term ? If so, our application tick period is less than 1msec (=20usec).

please check this picture image.

Regards,

Kz777

Kz777 said:

Your mentioned 1msec tick period mean, this each of 20usec term ? If so, our application tick period is less than 1msec (=20usec).

I don't really understand your question.  Your BIOS CLK tick occurs every 1 msec (unless you have changed it).  If your GPIO HWI takes 20 usec and you mask the CLK HWI for that duration, then a CLK tick HWI will potentially be delayed by 20 usec.  When this happens, the next CLK tick after that will happen at the regular 1 msec boundary (unless this one is also delayed by interrupt masking).

For example, if the normal CLK HWI would occur at 1000 usec, 2000 usec, 3000 usec, etc. (every 1 msec), and your GPIO HWI occurs at 999 usec and masks the CLK HWI for 20 usec, then the CLK HWI will be serviced at 1019 instead of the normal 1000.  But the next CLK HWI will happen at 2000, then 3000, etc., thereby keeping realtime.

If you had something mask the CLK HWI for 1100 usec, and that masking started at 999 usec, then the 1000 usec CLK HWI won't happen until 2009 usec, hence missing the occurrence of the 1000 usec tick, and it wouldn't catch up so CLK's realtime would be skewed. by 1 msec.

I hope this helps you answer your question.

Regards,

- Rob