RTOS/CC2640: Timer mysteriously stopped

Hector Urroz

Part Number: CC2640
Other Parts Discussed in Thread: SYSBIOS, CC2650, CC1350

Tool/software: TI-RTOS

We have a BLE application running TI-RTOS on the CC2640. It runs great, except that at some point things will freeze and the only way out is to power cycle by taking out the batteries.

I think I've narrowed down the problem to the RTC timer mysteriously stopping. Here's the info I've been able to gather, mostly from CCS register and POV views:

- I have two modes "good" and "bad". In good mode all is running perfectly, but at some point the CC2640 goes into bad mode, and freezes.
- In bad mode the CCS debugger shows that the ticks field in the clock module is stuck, doesn't move after pausing and resuming the debugger. In good mode, the ticks field goes up nicely as I pause/resume the debugger.
- In good mode I always see ISRPENDING 1 and VECTPENDING 010000 (16)
- in bad mode I always see ISRPENDING 1 and VECTPENDING 000000 (0)
- debugger also shows tickSource = ti.sysbios.knl.Clock.TickSource_TIMER
- I'm pretty sure we're using the AON_RTC (always on timer) at interrupt 20
- I don't think I'm using the builtin SysTick timer since the ENABLE bit in STCSR is set to 0 and STRVR and STCVR are are also zero.
- In good mode hwi shows all interrupts enabled, with our one pending interrupt 16
- In bad mode hwi shows all interrupts enabled, and none pending
- In bad mode we always see 1 or 2 IRPs pointing to ROM
- In good mode we seldom see IRPs pointing to ROM
- Hwi shows that all interrupts are running at the same priority, 255
- In both good and mode the timer at interrupt 20 appears as disabled in the Timer module
- We're using the AON_RTC (always on timer) at address 0x400092000
- In good mode the timer module shows the prevThreshold field moving along just fine
- In bad mode the timer module shows prevThreshold field stuck

Questions:
1) Why does the timer module show the state "disabled" in both good and bad modes? Is it because the debugger stops the clock?
2) What can cause the timer to become stuck?
3) Is it possible that we're getting too many stacked interrupts and we're breaking a stack or taking a bad return out of an ISR?

Any help would be much appreciated, thanks!

P.S. this is a dup of a question I posted in the BLE forum, but I think it's probably best discussed here. I'll close the other post, and sorry about cross-posting.

over 7 years ago

0 Alan DeMars over 7 years ago

TI__Mastermind 30830 points

1) The Timer Module's ROV view is broken and missleading. A bug was been filed about this issue a few months ago and a fix for it will be included in the next release of TI-RTOS.
2) I know of no reason that the RTC should stop. Other than using the RTC as the time base for the Clock and Seconds modules, is your application internally using some other feature of the RTC?
3) The Hwi module is designed to avoid the stack problem associated with an always pending interrupt. In the failed case, you can view the Task detailed ROV view and Hwi module ROV view to determine if any task stack or the interrupt stack has overflowed.

I think the BLE folks may have to track this down. The RTC halting may be the result of a confluence of hardware dynamics that they are aware of.

Alan

0 Hector Urroz over 7 years ago in reply to Alan DeMars

Intellectual 290 points

Hi Alan:

Just looked at the Hwi module ROV and saw the three hwiStack* fields all in red with no content. This is true for both the good and failed cases. Is that a clue that something's awry?

Thanks, Hector

0 Alan DeMars over 7 years ago in reply to Hector Urroz

TI__Mastermind 30830 points

Yes. If you hover the mouse over the red fields, a message such as "Overrun!" should be displayed.
You should increase the Hwi stack size. The Hwi stack is inherited from the C main() stack.
If using the TI/CCS compiler tools The "Program.stack" setting in your .cfg file is used to set the main stack size.
If using IAR tools, the main stack size is set in the .icf file.

Alan

0 Hector Urroz over 7 years ago in reply to Alan DeMars

Intellectual 290 points

I had previously doubled the size of the program stack to no effect. I'll try raising it again.=

When I hover over the hwiStack* I see "Error fetching Hwi stack info!" rather than an overflow message. I see this whether running successfully or after the failure. What could be causing trouble fetching the stack info?

0 Alan DeMars over 7 years ago in reply to Hector Urroz

TI__Mastermind 30830 points

Hmm. The error reported indicates memory corruption. It seems that something in the application is scribbling on the Hwi module's internal state structure.

If you open a memory view and type in "&ti_sysbios_family_arm_m3_Hwi_Module__state__V", you should see something like below:

0x2000011C 00000000 200022E8
0x20000130 00000000 20000134 20000134 2000013C 2000013C
0x20000144 ti_sysbios_family_arm_m3_Hwi_Module__state__V
0x20000144 00000000 20002272 200022E0 200022E4 20004FF8
0x20000158 20004C00 00000400 20000000 00000101 20001C80
0x2000016C 00000000 00000000 00000000

Notice that the value of 0x20004c00 is the address of the base of the Hwi stack and the value 0x00000400 is the size of the Hwi stack (1024 bytes).

In your memory view, meaningful values should be at the corresponding places in you Hwi module state. If not, then something is going horribly wrong in the application.

Placing a hardware watchpoint on writes to the address of the base of the Hwi stack might help reveal who the culprit is. Remember that at startup, the C initialization code will write to this address once, so the watchpoint will be always triggered once. But it should never be written again.

Alan

0 Hector Urroz over 7 years ago in reply to Alan DeMars

Intellectual 290 points

Thanks, I'll take a look at the stack itself.

Here's the dump you suggested, which looks ok to me. Do you see anything fishy?

ti_sysbios_family_arm_m3_Hwi_Module__state__V
0x00000000 0x20000CB2 0x20000D7C 0x20000D80 0x20004360
0x20003F68 0x00000400 0x20000000 0x00000101 0x20002BDC
0x00000000 0x00000000 0x00000000
ti_sysbios_knl_Clock_Module__state__V
0x0035F21A 0x00000000 0x20000960 0x20000A10 0x00000007
0x0035F221 0xC11F404E 0x00000000 0x00000001 0x20000AD8
0x20001E60
ti_sysbios_BIOS_Module__state__V
0x00000000 0x02DC6C00 0x00000000 0x00000000 0x200009C4
0x00000002 0x00000000 0x0000D569 0x0000E249
ti_sysbios_knl_Swi_Module__state__V
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x200009E0 0x00000000
ti_sysbios_family_arm_cc26xx_Timer_Module__state__V
0x00000000 0x20000960

0 Alan DeMars over 7 years ago in reply to Hector Urroz

TI__Mastermind 30830 points

I don't see anything wrong with the content of the module state structure. Not sure why you're getting that error report. ROV is internally complaining that it can't read the Hwi stack memory. Was the Hwi module view reporting the error when you did this memory dump?

Can you dump the memory beginning at address 0x20003f68? This is the base address of the Hwi stack.

Does the Task detailed view show the task stack depths properly?

Alan

0 Hector Urroz over 7 years ago in reply to Alan DeMars

Intellectual 290 points

Yes, the Hwi module view was reporting "error fetching" on the hwiStack* fields when I read the memory. Here's the stack dump. Just noticed that my stack base address is not as well aligned as yours, mine starts at 0x20003F68 and yours at 0x20004C00. Could that be a problem?

0 Hector Urroz over 7 years ago in reply to Hector Urroz

Intellectual 290 points

Sorry, here's the stack dump.

0 Hector Urroz over 7 years ago in reply to Hector Urroz

Intellectual 290 points

You asked about the detailed stack view and that does show all the stack* fields properly.

0 Alan DeMars over 7 years ago in reply to Hector Urroz

TI__Mastermind 30830 points

That's a fine looking stack. 8 byte alignment is all that is required. The "bebebebe" pattern is written at startup to help us determine how deep the stack gets. You've got lots of unused stack space.

0 Alan DeMars over 7 years ago in reply to Alan DeMars

TI__Mastermind 30830 points

Is it possible that the application has disabled interrupts and never re-enabled them? In the bad case, use the CCS Core Register view to dump the content of the CTRL_FAULT_BASE_PRI regster:

CTRL_FAULT_BASE_PRI 0x00000000 CM3 Special Registers [Core]

It should be all zeros. If the BASEPRI or PRIMASK fields are non-zero, then interrupts are disabled. If this is the case, you'll need to analyze your code to find out where Hwi_disable() is called without a matching Hwi_restore() call.

Alan

0 Hector Urroz over 7 years ago in reply to Alan DeMars

Intellectual 290 points

I think I might have looked for that before and didn't see trouble. Both before and after the freeze I see:

CTRL_FAULT_BASE_PRI 0x02000000 CM3 Special Registers [Core]
CONTROL 00000010 Control
FAULTMASK 00000000 Faultmask
BASEPRI 00000000 Basepri
PRIMASK 00000000 Primask

I think that 1 bit in the CONTROL part is ok, or should that be a zero?

0 Alan DeMars over 7 years ago in reply to Hector Urroz

TI__Mastermind 30830 points

I misspoke about it being all zeros. The Control value of 10 is ok. The other fields are good. Interrupts are enabled.
I'm almost out of ideas for today. You should probably beg for help from the BLE team as they should know under what conditions the RTC is halted.
You may need to put a hardware watchpoint on memory writes to the RTC control register to see if it is getting written to by a rogue thread.
I'd have to dig in deeper to figure out which bit in which register enables the counter. Perhaps you already know...

Alan

0 Hector Urroz over 7 years ago in reply to Alan DeMars

Intellectual 290 points

Thanks so much Alan! I owe you lunch if you're ever in Colorado, :-)

0 Hector Urroz over 7 years ago in reply to Hector Urroz

Intellectual 290 points

Hi Alan,

We think we found the problem. Here's a description from my co-developer, Dave Beal:

I think I have a fix for the bug. The problem is in the TI-RTOS file ti\tirtos_cc13xx_cc26xx_2_18_00_03\products\bios_6_45_02_31\packages\ti\sysbios\family\arm\cc26xx\Timer.c, in the function Timer_setThreshold(). This is the code that writes a timeout value into the RTC to implement the Task_sleep() function. There's code in there to handle the case where the timeout time it's being asked to set is in the past or less than 4/65536 of a second in the future; if so, it programs a value that is 4/65536 sec in the future. However, the HW manual says that it can take up to two 32KHz clock ticks for the register write to actually happen, so the less-than-4/65536-sec margin isn't quite enough. I added global variables to save the most recent timeout and current time values, and when the problem happened the requested timeout was always less than 4/65536 sec in the future. I changed the margin to 6/65536 sec, and the Remote has been running for more than an hour now. Before, it would consistently fail within a few minutes. I'm still a little confused though, because the HW manual says that the HW will generate an interrupt even if the timeout value being set is up to one second in the past; I don't understand why this didn't prevent the problem, but maybe there's a reason why the RTOS author didn't choose to rely on this.

Neither he nor I have seen the freeze since we implemented the change. What are your thoughts? Is this the root cause for the freeze?

Thanks, Hector

0 Alan DeMars over 7 years ago in reply to Hector Urroz

TI__Mastermind 30830 points

That code has been carefully scrutinized to handle just the situation you're encountering. Can you provide us with the exact CC2640 part numbers you're seeing the problem manifest itself on? I mean the info printed on the back of the chips themselves.

0 Hector Urroz over 7 years ago in reply to Alan DeMars

Intellectual 290 points

This is what's on the back of my chip:
CC2640
F128
TI 5CI
AL06 G4

0 Dave Beal over 7 years ago in reply to Hector Urroz

Intellectual 880 points

Hi Alan! I'm the guy who's working with Hector. My chip has exactly the same markings as his.

0 Alan DeMars over 7 years ago in reply to Dave Beal

TI__Mastermind 30830 points

Thanks! We've asked the chip design team to take a look. There's a lot of history on this topic.

Alan

0 Dave Beal over 7 years ago in reply to Alan DeMars

Intellectual 880 points

Thanks, Alan. We appreciate you digging into this.

0 Alan DeMars over 7 years ago in reply to Dave Beal

TI__Mastermind 30830 points

We'd like you to use the "SmartRF Flash Programmer 2" application to help us identify the chip version on your devices.

The tool is available here if you don't already have it installed:

http://www.ti.com/tool/flash-programmer

The info we need is shown in the read box below:

Alan

0 ScottG over 7 years ago in reply to Alan DeMars

TI__Mastermind 26780 points

Hector, Dave,

Can you please clarify if you are seeing the RTC counter stall, or if you are seeing that the RTC continues to count, but a timeout event was missed by software?

A quick way to see this is to open the CCS register view (View->Registers), expand the “AON_RTC” register set, and look at the SEC and SUBSEC registers. For example:

For the case where your app was stalling (before increasing the COMPARE_MARGIN), do you see that these registers continue to update, even though the app has stalled?

Thanks,
Scott

0 Hector Urroz over 7 years ago in reply to ScottG

Intellectual 290 points

Here's my info from flash programmer 2. I'll check on those RTC registers.

0 Hector Urroz over 7 years ago in reply to Hector Urroz

Intellectual 290 points

Hi Scott,

I checked the SEC and SUBSEC registers and and they do continue to update even as we're stalled.

Also, I think I mentioned this earlier, the ticks field in the clock module in ROV stays frozen when we're stalled.

Thanks, Hector

0 Dave Beal over 7 years ago in reply to ScottG

Intellectual 880 points

Hi Scott. Before increasing COMPARE_MARGIN from 4 to 6, when our app was stalled, we were seeing the RTC's SEC and SUBSEC registers still incrementing, but CH0CMP was in the past w.r.t (smaller than) SEC.SUBSEC and not changing. Now that we've increased COMPARE_MARGIN to 6, our app no longer stalls and we see all three registers changing, and CH0CMP is always in the future w.r.t SEC.SUBSEC.

0 ScottG over 7 years ago in reply to Dave Beal

TI__Mastermind 26780 points

Hi Hector, Dave,

Thank you for clarifying. These symptoms point to an RTC timeout event not being received by the CPU.

I have several questions:

Are you running on a custom board, or on a TI-development board? What are you using for your low frequency (LF) clock source?

Are you maybe programming the RTC directly in your program?

Have you modified the default configuration settings in the ccfg.c file? If yes, can you please attach that file?

Also, have you moved the default placement of this configuration structure?

Have you maybe changed the Hwi.disablePriority setting in your application configuration (.cfg) file? Or changed interrupt priority settings in some way such that an interrupt is firing at higher priority than the Hwi.disablePriority setting?

Can you please post your application .cfg file to this thread?

If you don’t want to post these files to the forum you can send me a friend request, and then you’ll be able to send these to me directly so that we can look at them…

Thanks,
Scott

0 Dave Beal over 7 years ago in reply to ScottG

Intellectual 880 points

Hi Scott -

It is a custom board. For the 32KHz clock, we are using an external crystal. The schematic says "32.768KHz +/- 100 ppm". We are not explicitly using the RTC in our code. We are using a couple GPIOs as interrupt sources, but I don't think we've made any changes to the default interrupt priorities. Our cfg file in pasted below. Changes are (probably) marked with my initials (DDB).

- Dave

/******************************************************************************

@file cc2640.cfg

@brief TI RTOS Configuration file for CC26xx

Imported Symbols

Note: These symbols are defined following the --cfgArgs option.

In IAR this is done at the end of the pre-build step. In CCS, this

is done in Properties->build->XDCtools-Advanced options->Configuration

script arguments. Multiple symbols can be used separating them by a

comma (",").

By default, TI RTOS builds with RTOS in ROM, interrupt vectors starting

at address 0x0 and uses ROM only kernel modules.

NO_ROM: When set to a non-zero value, RTOS builds in Flash instead

of ROM

OAD_IMG_A: When set to a non-zero value, interrupt vectors are set to

their expected location for on-chip OAD Image A.

OAD_IMG_B: When set to a non-zero value, interrupt vectors are set to

their expected location for on-chip OAD Image B.

OAD_IMG_E: When set to a non-zero value, interrupt vectors are set to

their expected location for external flash OAD.

USE_EVENTS: Build the RTOS Kernel Event module.

Group: WCS, BTS

Target Device: CC2650, CC2640, CC1350

******************************************************************************

Redistribution and use in source and binary forms, with or without

modification, are permitted provided that the following conditions

are met:

* Redistributions of source code must retain the above copyright

notice, this list of conditions and the following disclaimer.

* Redistributions in binary form must reproduce the above copyright

notice, this list of conditions and the following disclaimer in the

documentation and/or other materials provided with the distribution.

* Neither the name of Texas Instruments Incorporated nor the names of

its contributors may be used to endorse or promote products derived

from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR

CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,

PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;

OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,

WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR

OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,

EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

******************************************************************************

Release Name: ble_sdk_2_02_00_31

Release Date: 2016-06-16 18:57:29

*****************************************************************************/

/* ================ ROM configuration ================ */

* To use BIOS in flash, comment out the code block below.

/* DDB, 10/22/16 */

if (typeof NO_ROM == 'undefined' || (typeof NO_ROM != 'undefined' && NO_ROM == 0))

{

var ROM = xdc.useModule('ti.sysbios.rom.ROM');

if (Program.cpu.deviceName.match(/CC26/)) {

ROM.romName = ROM.CC2650;

}

else if (Program.cpu.deviceName.match(/CC13/)) {

ROM.romName = ROM.CC1350;

}

/* */

/* ================ Boot configuration ================ */

if (typeof NO_ROM == 'undefined' || (typeof NO_ROM != 'undefined' && NO_ROM == 0))

{

var Boot = xdc.useModule('ti.sysbios.family.arm.cc26xx.Boot');

}

* This module contains family specific Boot APIs and configuration settings.

* See the SYS/BIOS API guide for more information.

if (typeof NO_ROM == 'undefined' || (typeof NO_ROM != 'undefined' && NO_ROM == 0))

{

Boot.driverlibVersion = 2;

Boot.customerConfig = false;

}

/* ================ Clock configuration ================ */

var Clock = xdc.useModule('ti.sysbios.knl.Clock');

* When using Power and calibrateRCOSC is set to true, this should be set to 10.

* The timer used by the Clock module supports TickMode_DYNAMIC. This enables us

* to set the tick period to 10 us without generating the overhead of additional

* interrupts.

* Note: The calibrateRCOSC parameter is set within the Power configuration

* structure in the "Board.c" file.

Clock.tickPeriod = 10;

Clock.swiPriority = 5;

/* ================ Types configuration ================ */

var Types = xdc.useModule('xdc.runtime.Types');

* This module defines basic constants and types used throughout the

* xdc.runtime package.

/* ================ Defaults (module) configuration ================ */

var Defaults = xdc.useModule('xdc.runtime.Defaults');

* A flag to allow module names to be loaded on the target. Module name

* strings are placed in the .const section for debugging purposes.

* Pick one:

* - true (default)

* Setting this parameter to true will include name strings in the .const

* section so that Errors and Asserts are easier to debug.

* - false

* Setting this parameter to false will reduce footprint in the .const

* section. As a result, Error and Assert messages will contain an

* "unknown module" prefix instead of the actual module name.

* When using BIOS in ROM:

* This option must be set to false.

// Defaults.common$.namedModule = true;

Defaults.common$.namedModule = false;

/* Compile out all Assert's */

//Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;

/* Allow Mod_create() and Mod_construct() but not delete() or destruct() */

Defaults.common$.memoryPolicy = Types.CREATE_POLICY;

/* ================ Error configuration ================ */

var Error = xdc.useModule('xdc.runtime.Error');

* This function is called to handle all raised errors, but unlike

* Error.raiseHook, this function is responsible for completely handling the

* error with an appropriately initialized Error_Block.

* Pick one:

* - Error.policyDefault (default)

* Calls Error.raiseHook with an initialized Error_Block structure and logs

* the error using the module's logger.

* - Error.policySpin

* Simple alternative that traps on a while(1) loop for minimized target

* footprint.

* Using Error.policySpin, the Error.raiseHook will NOT called.

// DDB, 10/24/16

Error.policyFxn = Error.policyDefault;

// Error.policyFxn = Error.policySpin;

* If Error.policyFxn is set to Error.policyDefault, this function is called

* whenever an error is raised by the Error module.

* Pick one:

* - Error.print (default)

* Errors are formatted and output via System_printf() for easier

* debugging.

* - null

* Errors are trapped with a while(1) stub function. This option reduces

* code footprint.

* - non-null function

* Errors invoke custom user function. See the Error module documentation

* for more details.

Error.raiseHook = Error.print;

// DDB, 11/7/16

// Error.raiseHook = null;

// Error.raiseHook = "&smallErrorHook";

* If Error.policyFxn is set to Error.policyDefault, this option applies to the

* maximum number of times the Error.raiseHook function can be recursively

* invoked. This option limits the possibility of an infinite recursion that

* could lead to a stack overflow.

* The default value is 16.

Error.maxDepth = 2;

/* ================ Hwi configuration ================ */

var halHwi = xdc.useModule('ti.sysbios.hal.Hwi');

var m3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');

* Checks for Hwi (system) stack overruns while in the Idle loop.

* Pick one:

* - true (default)

* Checks the top word for system stack overflows during the idle loop and

* raises an Error if one is detected.

* - false

* Disabling the runtime check improves runtime performance and yields a

* reduced flash footprint.

// DDB, 10/24/16

halHwi.checkStackFlag = true;

// halHwi.checkStackFlag = false;

* The following options alter the system's behavior when a hardware exception

* is detected.

* Pick one:

* - Hwi.enableException = true

* This option causes the default m3Hwi.excHandlerFunc function to fully

* decode an exception and dump the registers to the system console.

* This option raises errors in the Error module and displays the

* exception in ROV.

* - Hwi.enableException = false

* This option reduces code footprint by not decoding or printing the

* exception to the system console.

* It however still raises errors in the Error module and displays the

* exception in ROV.

* - Hwi.excHandlerFunc = null

* This is the most aggressive option for code footprint savings; but it

* can difficult to debug exceptions. It reduces flash footprint by

* plugging in a default while(1) trap when exception occur. This option

* does not raise an error with the Error module.

// m3Hwi.enableException = true;

m3Hwi.enableException = false;

// DDB, 10/24/16

m3Hwi.excHookFunc = "&excHandlerHook";

// m3Hwi.excHandlerFunc = null;

* Enable hardware exception generation when dividing by zero.

* Pick one:

* - 0 (default)

* Disables hardware exceptions when dividing by zero

* - 1

* Enables hardware exceptions when dividing by zero

m3Hwi.nvicCCR.DIV_0_TRP = 0;

//m3Hwi.nvicCCR.DIV_0_TRP = 1;

* Enable hardware exception generation for invalid data alignment.

* Pick one:

* - 0 (default)

* Disables hardware exceptions for data alignment

* - 1

* Enables hardware exceptions for data alignment

m3Hwi.nvicCCR.UNALIGN_TRP = 0;

//m3Hwi.nvicCCR.UNALIGN_TRP = 1;

/* Put reset vector at start of Flash */

if (typeof OAD_IMG_A != 'undefined' && OAD_IMG_A == 1)

{

m3Hwi.resetVectorAddress = 0x0610;

}

else if (typeof OAD_IMG_B != 'undefined' && OAD_IMG_B == 1)

{

m3Hwi.resetVectorAddress = 0x6010;

}

else if (typeof OAD_IMG_E != 'undefined' && OAD_IMG_E == 1)

{

m3Hwi.resetVectorAddress = 0x1010;

}

else

{

m3Hwi.resetVectorAddress = 0x0;

}

/* Put interrupt vector at start of RAM so interrupts can be configured at runtime */

m3Hwi.vectorTableAddress = 0x20000000;

/* CC2650 has 50 interrupts */

m3Hwi.NUM_INTERRUPTS = 50;

/* ================ Idle configuration ================ */

var Idle = xdc.useModule('ti.sysbios.knl.Idle');

* The Idle module is used to specify a list of functions to be called when no

* other tasks are running in the system.

* Functions added here will be run continuously within the idle task.

* Function signature:

* Void func(Void);

// Idle.addFunc("&MyIdleFunction");

/* ================ Kernel (SYS/BIOS) configuration ================ */

var BIOS = xdc.useModule('ti.sysbios.BIOS');

* Enable asserts in the BIOS library.

* Pick one:

* - true (default)

* Enables asserts for debugging purposes.

* - false

* Disables asserts for a reduced code footprint and better performance.

* When using BIOS in ROM:

* This option must be set to false.

// DDB, 10/22/16 - Enabling this causes memory limits to be exceeded

// BIOS.assertsEnabled = true;

BIOS.assertsEnabled = false;

* Specify default heap size for BIOS.

if (typeof NO_ROM == 'undefined' || (typeof NO_ROM != 'undefined' && NO_ROM == 0))

{

BIOS.heapSize = 1668;

}

* A flag to determine if xdc.runtime sources are to be included in a custom

* built BIOS library.

* Pick one:

* - false (default)

* The pre-built xdc.runtime library is provided by the respective target

* used to build the application.

* - true

* xdc.runtime library sources are to be included in the custom BIOS

* library. This option yields the most efficient library in both code

* footprint and runtime performance.

//BIOS.includeXdcRuntime = false;

BIOS.includeXdcRuntime = true;

* The SYS/BIOS runtime is provided in the form of a library that is linked

* with the application. Several forms of this library are provided with the

* SYS/BIOS product.

* Pick one:

* - BIOS.LibType_Custom

* Custom built library that is highly optimized for code footprint and

* runtime performance.

* - BIOS.LibType_Debug

* Custom built library that is non-optimized that can be used to

* single-step through APIs with a debugger.

BIOS.libType = BIOS.LibType_Custom;

//BIOS.libType = BIOS.LibType_Debug;

* Runtime instance creation enable flag.

* Pick one:

* - true (default)

* Allows Mod_create() and Mod_delete() to be called at runtime which

* requires a default heap for dynamic memory allocation.

* - false

* Reduces code footprint by disallowing Mod_create() and Mod_delete() to

* be called at runtime. Object instances are constructed via

* Mod_construct() and destructed via Mod_destruct().

* When using BIOS in ROM:

* This option must be set to true.

BIOS.runtimeCreatesEnabled = true;

//BIOS.runtimeCreatesEnabled = false;

* Enable logs in the BIOS library.

* Pick one:

* - true (default)

* Enables logs for debugging purposes.

* - false

* Disables logging for reduced code footprint and improved runtime

* performance.

* When using BIOS in ROM:

* This option must be set to false.

// DDB, 10/22/16 - Enabling this causes memory limits to be exceeded

// BIOS.logsEnabled = true;

BIOS.logsEnabled = false;

BIOS.swiEnabled = true;

/* ================ Memory configuration ================ */

var Memory = xdc.useModule('xdc.runtime.Memory');

* The Memory module itself simply provides a common interface for any

* variety of system and application specific memory management policies

* implemented by the IHeap modules(Ex. HeapMem, HeapBuf).

/* Create a small "alloc-only" heap */

if (typeof NO_ROM != 'undefined' && NO_ROM != 0)

{

var HeapMin = xdc.useModule('xdc.runtime.HeapMin');

var heapMinParams = new HeapMin.Params;

heapMinParams.size = 1668;

var myHeapMin = HeapMin.create(heapMinParams);

Memory.defaultHeapInstance = myHeapMin;

}

/* ================ Program configuration ================ */

* Program.stack is ignored with IAR. Use the project options in

* IAR Embedded Workbench to alter the system stack size.

if (typeof NO_ROM == 'undefined' || (typeof NO_ROM != 'undefined' && NO_ROM == 0))

{

Program.stack = 1024;

Program.argSize = 0;

}

else

{

Program.stack = 512;

}

/* ================ Semaphore configuration ================ */

var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');

* Enables global support for Task priority pend queuing.

* Pick one:

* - true (default)

* This allows pending tasks to be serviced based on their task priority.

* - false

* Pending tasks are services based on first in, first out basis.

* When using BIOS in ROM:

* This option must be set to false.

// Semaphore.supportsPriority = true;

Semaphore.supportsPriority = false;

* Allows for the implicit posting of events through the semaphore,

* disable for additional code saving.

* Pick one:

* - true

* This allows the Semaphore module to post semaphores and events

* simultaneously.

* - false (default)

* Events must be explicitly posted to unblock tasks.

* When using BIOS in ROM:

* This option must be set to false.

//Semaphore.supportsEvents = true;

Semaphore.supportsEvents = false;

/* ================ Events configuration ================ */

if (typeof USE_EVENTS != 'undefined' && USE_EVENTS != 0)

{

var Events = xdc.useModule('ti.sysbios.knl.Event');

}

/* ================ Swi configuration ================ */

var Swi = xdc.useModule('ti.sysbios.knl.Swi');

* A software interrupt is an object that encapsulates a function to be

* executed and a priority. Software interrupts are prioritized, preempt tasks

* and are preempted by hardware interrupt service routines.

* This module is included to allow Swi's in a users' application.

Swi.numPriorities = 6;

/* ================ System configuration ================ */

var System = xdc.useModule('xdc.runtime.System');

* The Abort handler is called when the system exits abnormally.

* Pick one:

* - System.abortStd (default)

* Call the ANSI C Standard 'abort()' to terminate the application.

* - System.abortSpin

* A lightweight abort function that loops indefinitely in a while(1) trap

* function.

* - A custom abort handler

* A user-defined function. See the System module documentation for

* details.

// DDB, 10/24/16

// System.abortFxn = System.abortStd;

// System.abortFxn = System.abortSpin;

System.abortFxn = "&myAbortSystem";

* The Exit handler is called when the system exits normally.

* Pick one:

* - System.exitStd (default)

* Call the ANSI C Standard 'exit()' to terminate the application.

* - System.exitSpin

* A lightweight exit function that loops indefinitely in a while(1) trap

* function.

* - A custom exit function

* A user-defined function. See the System module documentation for

* details.

// DDB, 10/24/16

// System.exitFxn = System.exitStd;

// System.exitFxn = System.exitSpin;

System.exitFxn = "&myExitSystem";

* Minimize exit handler array in the System module. The System module includes

* an array of functions that are registered with System_atexit() which is

* called by System_exit(). The default value is 8.

System.maxAtexitHandlers = 0;

* The System.SupportProxy defines a low-level implementation of System

* functions such as System_printf(), System_flush(), etc.

* Pick one pair:

* - SysMin

* This module maintains an internal configurable circular buffer that

* stores the output until System_flush() is called.

* The size of the circular buffer is set via SysMin.bufSize.

* - SysCallback

* SysCallback allows for user-defined implementations for System APIs.

* The SysCallback support proxy has a smaller code footprint and can be

* used to supply custom System_printf services.

* The default SysCallback functions point to stub functions. See the

* SysCallback module's documentation.

//var SysMin = xdc.useModule('xdc.runtime.SysMin');

//SysMin.bufSize = 128;

//System.SupportProxy = SysMin;

var SysCallback = xdc.useModule('xdc.runtime.SysCallback');

System.SupportProxy = SysCallback;

//SysCallback.abortFxn = "&myUserAbort";

//SysCallback.exitFxn = "&myUserExit";

//SysCallback.flushFxn = "&myUserFlush";

//SysCallback.putchFxn = "&myUserPutch";

//SysCallback.readyFxn = "&myUserReady";

/* ================ Task configuration ================ */

var Task = xdc.useModule('ti.sysbios.knl.Task');

* Check task stacks for overflow conditions.

* Pick one:

* - true (default)

* Enables runtime checks for task stack overflow conditions during

* context switching ("from" and "to")

* - false

* Disables runtime checks for task stack overflow conditions.

* When using BIOS in ROM:

* This option must be set to false.

// Task.checkStackFlag = true;

Task.checkStackFlag = false;

* Set the default task stack size when creating tasks.

* The default is dependent on the device being used. Reducing the default stack

* size yields greater memory savings.

Task.defaultStackSize = 512;

* Enables the idle task.

* Pick one:

* - true (default)

* Creates a task with priority of 0 which calls idle hook functions. This

* option must be set to true to gain power savings provided by the Power

* module.

* - false

* No idle task is created. This option consumes less memory as no

* additional default task stack is needed.

* To gain power savings by the Power module without having the idle task,

* add Idle.run as the Task.allBlockedFunc.

Task.enableIdleTask = true;

//Task.enableIdleTask = false;

//Task.allBlockedFunc = Idle.run;

* If Task.enableIdleTask is set to true, this option sets the idle task's

* stack size.

* Reducing the idle stack size yields greater memory savings.

Task.idleTaskStackSize = 512;

* Reduce the number of task priorities.

* The default is 16.

* Decreasing the number of task priorities yield memory savings.

Task.numPriorities = 6;

/* ================ Text configuration ================ */

var Text = xdc.useModule('xdc.runtime.Text');

* These strings are placed in the .const section. Setting this parameter to

* false will save space in the .const section. Error, Assert and Log messages

* will print raw ids and args instead of a formatted message.

* Pick one:

* - true (default)

* This option loads test string into the .const for easier debugging.

* - false

* This option reduces the .const footprint.

// Text.isLoaded = true;

Text.isLoaded = false;

/* ================ TI-RTOS middleware configuration ================ */

var mwConfig = xdc.useModule('ti.mw.Config');

* Include TI-RTOS middleware libraries

/* ================ TI-RTOS drivers' configuration ================ */

var driversConfig = xdc.useModule('ti.drivers.Config');

* Include TI-RTOS drivers

* Pick one:

* - driversConfig.LibType_NonInstrumented (default)

* Use TI-RTOS drivers library optimized for footprint and performance

* without asserts or logs.

* - driversConfig.LibType_Instrumented

* Use TI-RTOS drivers library for debugging with asserts and logs enabled.

driversConfig.libType = driversConfig.LibType_NonInstrumented;

//driversConfig.libType = driversConfig.LibType_Instrumented;

// Remaining Modules

var Diags = xdc.useModule('xdc.runtime.Diags');

var Main = xdc.useModule('xdc.runtime.Main');

var Reset = xdc.useModule('xdc.runtime.Reset');

0 ScottG over 7 years ago in reply to Dave Beal

TI__Mastermind 26780 points

Dave,

Thanks for the additional info, and for your .cfg file.

Can you please also attach the ccfg.c file for your project?

One other thing we’re wondering is if you are linking to the pre-built driverlib library, or if maybe you have rebuilt it, or are building the sources directly as part of the app? And is it possible for you to send us directly (using the forum friend mechanism) your application out file so that we can disassemble a couple of critical functions?

Thanks,
Scott

0 Dave Beal over 7 years ago in reply to ScottG

Intellectual 880 points

HI Scott -

The only change that we have made to drivers is adding "#define Display_DISABLE_ALL 1" to the top of the Display.h file, because trying to write to the display that doesn't exist on our custom board seemed to be causing BLE performance problems.

I'll have to check with our customer to see if it's OK to send the application out file.

Our ccfg.c file is below.

- Dave

/******************************************************************************
* Filename: ccfg.c
* Revised: $Date: 2016-01-14 13:41:44 +0100 (to, 14 jan 2016) $
* Revision: $Revision: 16602 $
*
* Description: Customer Configuration for CC26xx device family (HW rev 2).
*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/

#include <stdint.h>
#include <inc/hw_types.h>
#include <inc/hw_ccfg.h>
#include <inc/hw_ccfg_simple_struct.h>

//*****************************************************************************
//
// Introduction
//
// This file contains fields used by Boot ROM, startup code, and SW radio
// stacks to configure chip behavior.
//
// Fields are documented in more details in hw_ccfg.h and CCFG.html in
// DriverLib documentation (doc_overview.html -> CPU Domain Memory Map -> CCFG).
//
//*****************************************************************************

//*****************************************************************************
//
// Set the values of the individual bit fields.
//
//*****************************************************************************

//#####################################
// Alternative DC/DC settings
//#####################################

#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING
#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0 // Alternative DC/DC setting enabled
// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x1 // Alternative DC/DC setting disabled
#endif

#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN
#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0x8 // 2.25V
#endif

#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN
#define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0 // Disable
// #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x1 // Enable
#endif

#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK
#define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x2 // 39mA
#endif

//#####################################
// XOSC override settings
//#####################################

#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR
// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x0 // Enable override
#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1 // Disable override
#endif

#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT
#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 0x0 // Delta = 0
#endif

#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET
#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0 // Delta = 0
#endif

#ifndef SET_CCFG_MODE_CONF_1_XOSC_MAX_START
#define SET_CCFG_MODE_CONF_1_XOSC_MAX_START 0x10 // 1600us
#endif

//#####################################
// Power settings
//#####################################

#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA
#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF // Signed delta value +1 to apply to the VDDR_TRIM_SLEEP target (0xF=-1=default=no compensation)
#endif

#ifndef SET_CCFG_MODE_CONF_DCDC_RECHARGE
#define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x0 // Use the DC/DC during recharge in powerdown
// #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x1 // Do not use the DC/DC during recharge in powerdown
#endif

#ifndef SET_CCFG_MODE_CONF_DCDC_ACTIVE
#define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x0 // Use the DC/DC during active mode
// #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x1 // Do not use the DC/DC during active mode
#endif

#ifndef SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL
// #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x0 // VDDS BOD level is 2.0V
#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // VDDS BOD level is 1.8V (or 1.65V for external regulator mode)
#endif

#ifndef SET_CCFG_MODE_CONF_VDDR_CAP
#define SET_CCFG_MODE_CONF_VDDR_CAP 0x3A // Unsigned 8-bit integer representing the min. decoupling capacitance on VDDR in units of 100nF
#endif

#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC
#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1 // Temperature compensation on VDDR sleep trim disabled (default)
// #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x0 // Temperature compensation on VDDR sleep trim enabled
#endif

//#####################################
// Clock settings
//#####################################

#ifndef SET_CCFG_MODE_CONF_SCLK_LF_OPTION
// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x0 // LF clock derived from High Frequency XOSC
// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x1 // External LF clock
#define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC
// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC
#endif

#ifndef SET_CCFG_MODE_CONF_XOSC_CAP_MOD
// #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x0 // Apply cap-array delta
#define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x1 // Don't apply cap-array delta
#endif

#ifndef SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA
#define SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF // Signed 8-bit value, directly modifying trimmed XOSC cap-array value
#endif

#ifndef SET_CCFG_EXT_LF_CLK_DIO
#define SET_CCFG_EXT_LF_CLK_DIO 0x01 // DIO number if using external LF clock
#endif

#ifndef SET_CCFG_EXT_LF_CLK_RTC_INCREMENT
#define SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 0x800000 // RTC increment representing the external LF clock frequency
#endif

//#####################################
// Special HF clock source setting
//#####################################
#ifndef SET_CCFG_MODE_CONF_XOSC_FREQ
// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x1 // Use HPOSC as HF source (if executing on a HPOSC chip, otherwise using default (=0x3))
// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x2 // HF source is a 48 MHz xtal
#define SET_CCFG_MODE_CONF_XOSC_FREQ 0x3 // HF source is a 24 MHz xtal (default)
#endif

//#####################################
// Bootloader settings
//#####################################

#ifndef SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE
#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00 // Disable ROM boot loader
// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader
#endif

#ifndef SET_CCFG_BL_CONFIG_BL_LEVEL
// #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x0 // Active low to open boot loader backdoor
#define SET_CCFG_BL_CONFIG_BL_LEVEL 0x1 // Active high to open boot loader backdoor
#endif

#ifndef SET_CCFG_BL_CONFIG_BL_PIN_NUMBER
#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0xFF // DIO number for boot loader backdoor
#endif

#ifndef SET_CCFG_BL_CONFIG_BL_ENABLE
// #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 // Enabled boot loader backdoor
#define SET_CCFG_BL_CONFIG_BL_ENABLE 0xFF // Disabled boot loader backdoor
#endif

//#####################################
// Debug access settings
//#####################################

#ifndef SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE
#define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0x00 // Disable unlocking of TI FA option.
// #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0xC5 // Enable unlocking of TI FA option with the unlock code
#endif

#ifndef SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE
// #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0x00 // Access disabled
#define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
#endif

#ifndef SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE
#define SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE 0x00 // Access disabled
// #define SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
#endif

#ifndef SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE
// #define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00 // Access disabled
#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
#endif

#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE
#define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0x00 // Access disabled
// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
#endif

#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE
#define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0x00 // Access disabled
// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
#endif

#ifndef SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE
#define SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE 0x00 // Access disabled
// #define SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
#endif

//#####################################
// Alternative IEEE 802.15.4 MAC address
//#####################################
#ifndef SET_CCFG_IEEE_MAC_0
#define SET_CCFG_IEEE_MAC_0 0xFFFFFFFF // Bits [31:0]
#endif

#ifndef SET_CCFG_IEEE_MAC_1
#define SET_CCFG_IEEE_MAC_1 0xFFFFFFFF // Bits [63:32]
#endif

//#####################################
// Alternative BLE address
//#####################################
#ifndef SET_CCFG_IEEE_BLE_0
#define SET_CCFG_IEEE_BLE_0 0xFFFFFFFF // Bits [31:0]
#endif

#ifndef SET_CCFG_IEEE_BLE_1
#define SET_CCFG_IEEE_BLE_1 0xFFFFFFFF // Bits [63:32]
#endif

//#####################################
// Flash erase settings
//#####################################

#ifndef SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N
// #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x0 // Any chip erase request detected during boot will be ignored
#define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x1 // Any chip erase request detected during boot will be performed by the boot FW
#endif

#ifndef SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N
// #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x0 // Disable the boot loader bank erase function
#define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x1 // Enable the boot loader bank erase function
#endif

//#####################################
// Flash image valid
//#####################################
#ifndef SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID
#define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 0x00000000 // Flash image is valid
// #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID <non-zero> // Flash image is invalid, call bootloader
#endif

//#####################################
// Flash sector write protection
//#####################################
#ifndef SET_CCFG_CCFG_PROT_31_0
#define SET_CCFG_CCFG_PROT_31_0 0xFFFFFFFF
#endif

#ifndef SET_CCFG_CCFG_PROT_63_32
#define SET_CCFG_CCFG_PROT_63_32 0xFFFFFFFF
#endif

#ifndef SET_CCFG_CCFG_PROT_95_64
#define SET_CCFG_CCFG_PROT_95_64 0xFFFFFFFF
#endif

#ifndef SET_CCFG_CCFG_PROT_127_96
#define SET_CCFG_CCFG_PROT_127_96 0xFFFFFFFF
#endif

//#####################################
// Select between cache or GPRAM
//#####################################
#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM
// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0 // Cache is disabled and GPRAM is available at 0x11000000-0x11001FFF
#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1 // Cache is enabled and GPRAM is disabled (unavailable)
#endif

//*****************************************************************************
//
// CCFG values that should not be modified.
//
//*****************************************************************************
#define SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058
#define SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS 0x3FFF

#define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x1
#define SET_CCFG_MODE_CONF_RTC_COMP 0x1
#define SET_CCFG_MODE_CONF_HF_COMP 0x1

#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 0xFF
#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 0xFF
#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 0xFF
#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 0xFF

#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 0xFF
#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 0xFF
#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 0xFF
#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 0xFF

#define SET_CCFG_RTC_OFFSET_RTC_COMP_P0 0xFFFF
#define SET_CCFG_RTC_OFFSET_RTC_COMP_P1 0xFF
#define SET_CCFG_RTC_OFFSET_RTC_COMP_P2 0xFF

#define SET_CCFG_FREQ_OFFSET_HF_COMP_P0 0xFFFF
#define SET_CCFG_FREQ_OFFSET_HF_COMP_P1 0xFF
#define SET_CCFG_FREQ_OFFSET_HF_COMP_P2 0xFF

//*****************************************************************************
//
// Concatenate bit fields to words.
// DO NOT EDIT!
//
//*****************************************************************************
#define DEFAULT_CCFG_O_EXT_LF_CLK ( \
( ((uint32_t)( SET_CCFG_EXT_LF_CLK_DIO << CCFG_EXT_LF_CLK_DIO_S )) | ~CCFG_EXT_LF_CLK_DIO_M ) & \
( ((uint32_t)( SET_CCFG_EXT_LF_CLK_RTC_INCREMENT << CCFG_EXT_LF_CLK_RTC_INCREMENT_S )) | ~CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) )

#define DEFAULT_CCFG_MODE_CONF_1 ( \
( ((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN << CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S )) | ~CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN << CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S )) | ~CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK << CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S )) | ~CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT << CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S )) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET << CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S )) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_1_XOSC_MAX_START << CCFG_MODE_CONF_1_XOSC_MAX_START_S )) | ~CCFG_MODE_CONF_1_XOSC_MAX_START_M ) )

#define DEFAULT_CCFG_SIZE_AND_DIS_FLAGS ( \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG << CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M ) & \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS << CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M ) & \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM << CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) & \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING << CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M ) & \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR << CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) )

#define DEFAULT_CCFG_MODE_CONF ( \
( ((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S )) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_DCDC_RECHARGE << CCFG_MODE_CONF_DCDC_RECHARGE_S )) | ~CCFG_MODE_CONF_DCDC_RECHARGE_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_DCDC_ACTIVE << CCFG_MODE_CONF_DCDC_ACTIVE_S )) | ~CCFG_MODE_CONF_DCDC_ACTIVE_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_VDDR_EXT_LOAD << CCFG_MODE_CONF_VDDR_EXT_LOAD_S )) | ~CCFG_MODE_CONF_VDDR_EXT_LOAD_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL << CCFG_MODE_CONF_VDDS_BOD_LEVEL_S )) | ~CCFG_MODE_CONF_VDDS_BOD_LEVEL_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_SCLK_LF_OPTION << CCFG_MODE_CONF_SCLK_LF_OPTION_S )) | ~CCFG_MODE_CONF_SCLK_LF_OPTION_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S )) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_RTC_COMP << CCFG_MODE_CONF_RTC_COMP_S )) | ~CCFG_MODE_CONF_RTC_COMP_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_XOSC_FREQ << CCFG_MODE_CONF_XOSC_FREQ_S )) | ~CCFG_MODE_CONF_XOSC_FREQ_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAP_MOD << CCFG_MODE_CONF_XOSC_CAP_MOD_S )) | ~CCFG_MODE_CONF_XOSC_CAP_MOD_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_HF_COMP << CCFG_MODE_CONF_HF_COMP_S )) | ~CCFG_MODE_CONF_HF_COMP_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S )) | ~CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ) & \
( ((uint32_t)( SET_CCFG_MODE_CONF_VDDR_CAP << CCFG_MODE_CONF_VDDR_CAP_S )) | ~CCFG_MODE_CONF_VDDR_CAP_M ) )

#define DEFAULT_CCFG_VOLT_LOAD_0 ( \
( ((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 << CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S )) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M ) & \
( ((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 << CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S )) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M ) & \
( ((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 << CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S )) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M ) & \
( ((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 << CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S )) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M ) )

#define DEFAULT_CCFG_VOLT_LOAD_1 ( \
( ((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 << CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S )) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M ) & \
( ((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 << CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S )) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M ) & \
( ((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 << CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S )) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M ) & \
( ((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 << CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S )) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M ) )

#define DEFAULT_CCFG_RTC_OFFSET ( \
( ((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P0 << CCFG_RTC_OFFSET_RTC_COMP_P0_S )) | ~CCFG_RTC_OFFSET_RTC_COMP_P0_M ) & \
( ((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P1 << CCFG_RTC_OFFSET_RTC_COMP_P1_S )) | ~CCFG_RTC_OFFSET_RTC_COMP_P1_M ) & \
( ((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P2 << CCFG_RTC_OFFSET_RTC_COMP_P2_S )) | ~CCFG_RTC_OFFSET_RTC_COMP_P2_M ) )

#define DEFAULT_CCFG_FREQ_OFFSET ( \
( ((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P0 << CCFG_FREQ_OFFSET_HF_COMP_P0_S )) | ~CCFG_FREQ_OFFSET_HF_COMP_P0_M ) & \
( ((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P1 << CCFG_FREQ_OFFSET_HF_COMP_P1_S )) | ~CCFG_FREQ_OFFSET_HF_COMP_P1_M ) & \
( ((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P2 << CCFG_FREQ_OFFSET_HF_COMP_P2_S )) | ~CCFG_FREQ_OFFSET_HF_COMP_P2_M ) )

#define DEFAULT_CCFG_IEEE_MAC_0 SET_CCFG_IEEE_MAC_0
#define DEFAULT_CCFG_IEEE_MAC_1 SET_CCFG_IEEE_MAC_1
#define DEFAULT_CCFG_IEEE_BLE_0 SET_CCFG_IEEE_BLE_0
#define DEFAULT_CCFG_IEEE_BLE_1 SET_CCFG_IEEE_BLE_1

#define DEFAULT_CCFG_BL_CONFIG ( \
( ((uint32_t)( SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE << CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S )) | ~CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M ) & \
( ((uint32_t)( SET_CCFG_BL_CONFIG_BL_LEVEL << CCFG_BL_CONFIG_BL_LEVEL_S )) | ~CCFG_BL_CONFIG_BL_LEVEL_M ) & \
( ((uint32_t)( SET_CCFG_BL_CONFIG_BL_PIN_NUMBER << CCFG_BL_CONFIG_BL_PIN_NUMBER_S )) | ~CCFG_BL_CONFIG_BL_PIN_NUMBER_M ) & \
( ((uint32_t)( SET_CCFG_BL_CONFIG_BL_ENABLE << CCFG_BL_CONFIG_BL_ENABLE_S )) | ~CCFG_BL_CONFIG_BL_ENABLE_M ) )

#define DEFAULT_CCFG_ERASE_CONF ( \
( ((uint32_t)( SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N << CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S )) | ~CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M ) & \
( ((uint32_t)( SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N << CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S )) | ~CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M ) )

#define DEFAULT_CCFG_CCFG_TI_OPTIONS ( \
( ((uint32_t)( SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE << CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S )) | ~CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M ) )

#define DEFAULT_CCFG_CCFG_TAP_DAP_0 ( \
( ((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S )) | ~CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M ) & \
( ((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE << CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_S )) | ~CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_M ) & \
( ((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE << CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S )) | ~CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M ) )

#define DEFAULT_CCFG_CCFG_TAP_DAP_1 ( \
( ((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE << CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S )) | ~CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M ) & \
( ((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE << CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S )) | ~CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M ) & \
( ((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE << CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_S )) | ~CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_M ) )

#define DEFAULT_CCFG_IMAGE_VALID_CONF ( \
( ((uint32_t)( SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID << CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S )) | ~CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M ) )

#define DEFAULT_CCFG_CCFG_PROT_31_0 SET_CCFG_CCFG_PROT_31_0
#define DEFAULT_CCFG_CCFG_PROT_63_32 SET_CCFG_CCFG_PROT_63_32
#define DEFAULT_CCFG_CCFG_PROT_95_64 SET_CCFG_CCFG_PROT_95_64
#define DEFAULT_CCFG_CCFG_PROT_127_96 SET_CCFG_CCFG_PROT_127_96

//*****************************************************************************
//
// Customer Configuration Area in Lock Page
//
//*****************************************************************************
#if defined(__IAR_SYSTEMS_ICC__)
__root const ccfg_t __ccfg @ ".ccfg" =
#elif defined(__TI_COMPILER_VERSION__)
#pragma DATA_SECTION(__ccfg, ".ccfg")
#pragma RETAIN(__ccfg)
const ccfg_t __ccfg =
#else
const ccfg_t __ccfg __attribute__((section(".ccfg"))) __attribute__((used)) =
#endif
{ // Mapped to address
DEFAULT_CCFG_O_EXT_LF_CLK , // 0x50003FA8 (0x50003xxx maps to last
DEFAULT_CCFG_MODE_CONF_1 , // 0x50003FAC sector in FLASH.
DEFAULT_CCFG_SIZE_AND_DIS_FLAGS , // 0x50003FB0 Independent of FLASH size)
DEFAULT_CCFG_MODE_CONF , // 0x50003FB4
DEFAULT_CCFG_VOLT_LOAD_0 , // 0x50003FB8
DEFAULT_CCFG_VOLT_LOAD_1 , // 0x50003FBC
DEFAULT_CCFG_RTC_OFFSET , // 0x50003FC0
DEFAULT_CCFG_FREQ_OFFSET , // 0x50003FC4
DEFAULT_CCFG_IEEE_MAC_0 , // 0x50003FC8
DEFAULT_CCFG_IEEE_MAC_1 , // 0x50003FCC
DEFAULT_CCFG_IEEE_BLE_0 , // 0x50003FD0
DEFAULT_CCFG_IEEE_BLE_1 , // 0x50003FD4
DEFAULT_CCFG_BL_CONFIG , // 0x50003FD8
DEFAULT_CCFG_ERASE_CONF , // 0x50003FDC
DEFAULT_CCFG_CCFG_TI_OPTIONS , // 0x50003FE0
DEFAULT_CCFG_CCFG_TAP_DAP_0 , // 0x50003FE4
DEFAULT_CCFG_CCFG_TAP_DAP_1 , // 0x50003FE8
DEFAULT_CCFG_IMAGE_VALID_CONF , // 0x50003FEC
DEFAULT_CCFG_CCFG_PROT_31_0 , // 0x50003FF0
DEFAULT_CCFG_CCFG_PROT_63_32 , // 0x50003FF4
DEFAULT_CCFG_CCFG_PROT_95_64 , // 0x50003FF8
DEFAULT_CCFG_CCFG_PROT_127_96 , // 0x50003FFC
};

0 ScottG over 7 years ago in reply to Dave Beal

TI__Mastermind 26780 points

Thanks Dave.

Just to be clear, you are not modifying or rebuilding driverlib either? Meaning the “cc26xxware_2_23_02_16941” component?

And one other thing, for the failing case can you please show the VIMS STAT and CTL register values? These are similarly viewable in the CCS register view, as the AON_RTC registers.

Thanks,
Scott

0 Dave Beal over 7 years ago in reply to ScottG

Intellectual 880 points

Hi Scott -

No, the only things we are (intentionally) building in CCS is our app and the BLE stack app.

Here are the VIMS registers at the time of the Timer failure:

0 ScottG over 7 years ago in reply to Dave Beal

TI__Mastermind 26780 points

Hi Dave,

OK, thanks for this, and for the other info you’ve been sending. These register values are as expected.

We’ve been trying to recreate a failure with our timing stress tests today and so far have not seen any failures. The tests are continuing to run on two boards overnight. We’re trying to determine what might be unique in the configuration and timing of your app that is requiring an increased compare margin.

If you are able to send us the .out file that might help to see if there is something different with respect to compiler optimizations that might be in play.

Thanks, and regards,
Scott

0 ScottG over 7 years ago in reply to ScottG

TI__Mastermind 26780 points

Hi Dave,

One more request. For the case where you see an app stall, can you please post a screenshot showing all the AON_RTC register values?

Thanks,
Scott

0 Dave Beal over 7 years ago in reply to ScottG

Intellectual 880 points

Hi Scott -

I've added screenshots of the AON_RTC regs along with the states of the Tasks and Clocks in our system when the problem occurs. After it's in the broken state, allowing the system to run and then pausing it causes only the RTC's SEC and SUBSEC registers to change; none of the others (including CH0CMP) changes once we're broken.

This problem has been very flaky for us, too. It sometimes happens every few minutes of run time, and at other times doesn't happen for weeks. In recreating it today, the device first ran for a half hour without a problem. Then I used a different BLE device for it to exchange data with, and it failed in 0x61 seconds (as the AON_RTC.CH0CMP register shows).

0 ScottG over 7 years ago in reply to Dave Beal

TI__Mastermind 26780 points

Hi Dave,

OK, thanks again.

Can you please attach ROV screenshots for the Hwi module when the stall occurs, specifically the ‘Detailed’ and ‘Module’ tabs?

Also, I’ve been wondering how you decided to change the compare margin value from “4” to “6”. Did you see failures at “5”?

Thanks,
Scott

0 Dave Beal over 7 years ago in reply to ScottG

Intellectual 880 points

HI Scott -

Shots of the Hwi tabs are below. No, we never tried COMPARE_MARGIN of 5. Also, I have our customer's permission to send our .out file to you.

0 ScottG over 7 years ago in reply to Dave Beal

TI__Mastermind 26780 points

Hi Dave,

Thanks for sending these. In the module view, a red indication by ROV usually means an error occurred when reading/interpreting the field. Is there any text shown besides the red boxes?

Or, if you hover over one of them is there a pop up message?

If you start the app, run and halt while the app is still running OK, do you still see error indications for these fields?

And if you click on the BIOS module in ROV and select scan for errors, what is indicated?

Thanks,
Scott

0 Hector Urroz over 7 years ago in reply to ScottG

Intellectual 290 points

Hi Scott, I went thru this with Alan in an earlier part of this thread. The text shown over the red boxes is "Error fetching Hwi stack info!". The scan for errors messages in the BIOS ROV has the same message repeated several times. These message show up also when the app is running OK.

Thanks,

Hector

0 Dave Beal over 6 years ago in reply to ScottG

Intellectual 880 points

Hi Scott -

In a private message to me, you asked "One more thing I wanted to clarify with you is: if you've checked that the RTC is counting at a rate that you expect. For example, if you look at the seconds count in CCS, and run for X seconds and halt, do you see the expected increment of X in the seconds count?".

Yes. After the problem occurs, if I pause execution in the CCS Debugger, note the value of AON_RTC.SEC, let execution resume for 60 seconds and then pause it again, the value in the SEC register has advanced by 0x3C.

0 ScottG over 6 years ago in reply to Dave Beal

TI__Mastermind 26780 points

As a follow-up to close out this thread…

After a root cause analysis a precise timing scenario was found where a compare margin value of “4” could be insufficient. But a compare margin value of “6” will avoid the problem.

The fix for this issue will be tracked with bug ID: SYSBIOS-383

Processors

Processors forum

RTOS/CC2640: Timer mysteriously stopped