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RTOS/AM5726: GPMC

Michelle Le
Prodigy 60 points
Part Number: AM5726

Tool/software: TI-RTOS

Hello,

I am working on AM5726. The code is running on A15. I try to talk to FPGA through the GPMC interface. The issue is I can't access to L3 Q1 memory. I am using TI-RTOS.  I think I should modify the .cfg file, but I don't know how to do that since I am brand new to TI-RTOS.  So does anyone can give me some ideas?

The code was failed on the following statement.

HW_WR_REG32(0x18000105, 0x000001).

Thanks

  • 0
    TI__Guru* 96960 points
    I've moved your thread to the device forum.

    Todd
  • 0
    TI__Guru** 114410 points
    Michelle,

    We don`t have ea GPMC interface connected to any memory device on the AM572xx GP EVM and the on the AM572x IDK EVM, the GPMC pins only go to a expansion header so there is no example for GPMC that we support in the SDK for these platforms.

    However, we have a automotive qualified variant of this silicon which is memory and pin compatible and their hardware platform has a NOR flash memory connected to GPMC. For your reference to access GPMC from ARM, you can refer to the example provided here:
    pdk_am57xx_1_0_x\packages\ti\csl\example\gpmc\nor_read_write

    If you look at the code, it alreaady has macros defined to build this for AM57xx platform (TDAxx and DRA7xx are the auto variants so you can ignore that code).

    From what I can see there is no additional MMU setting to access this region. NOR flash is direct addressable like in case of FPGA so initialization of GPMC should be similar.

    Regards,
    Rahul