VOLIB CCS4 RTSC

Hi Rob,

True, we don't yet have CCS projects in VoLIB for the components and our testing was performed exclusively on CCSv3.  We are in the process of adding CCSv4 projects, amongst other features, for our next release. This release will (obviously) be thoroughly tested on CCSv4.

Unfortunately, the next release is tentatively scheduled for Q3 2011 and this won't help you now.  As such, allow us a day or two to devise a solution for you that you may use moving forward - and that will tie in with our plans for the next release.

Please check back towards the end of this week.  We should have a solution in line by then.

Best Regards,

Charlie

Thanks, Charlie.

I have been able to setup a project which kind of works, at least compiles the two test source files, tstgmp.c and tdusim.c. I had to set the -ml and -mg compiler options. It now will not link properly, depening on my project Properties>C/C++ Build>Tool Settings>C5500 compiler>Basic Oprions>Device+Optional revision of target silicon selction (5505 or <blank>) I get one of two error reports.

5505 gets:

'Building target: z.out'

'Invoking: Linker'

"C:/Program Files/Texas Instruments/C5500 Code Generation Tools 4.3.5/bin/cl55" -v5505 -g --gcc --define=ti_targets_C55_large --diag_warning=225 --large_memory_model --ptrdiff_size=16 --algebraic --memory_model=large -z -m"z.map" --warn_sections -i"C:/Program Files/Texas Instruments/C5500 Code Generation Tools 4.3.5/lib" -i"C:/Program Files/Texas Instruments/C5500 Code Generation Tools 4.3.5/include" --reread_libs --rom_model -o "z.out" -l"./configPkg/linker.cmd" "./tstgmp.obj" "./tdusim.obj" -l"libc.a"

<Linking>

fatal error: file "./tstgmp.obj" specifies "C55x CPU Rev 3.x", which is not

compatible with "C55x CPU Rev 2.x" specified in a previous file or on the

command line

'Invoking: Linker'

"C:/Program Files/Texas Instruments/C5500 Code Generation Tools 4.3.5/bin/cl55" -g --gcc --define=ti_targets_C55_large --diag_warning=225 --large_memory_model --ptrdiff_size=16 --algebraic --memory_model=large -z -m"z.map" --warn_sections -i"C:/Program Files/Texas Instruments/C5500 Code Generation Tools 4.3.5/lib" -i"C:/Program Files/Texas Instruments/C5500 Code Generation Tools 4.3.5/include" --reread_libs --rom_model -o "z.out" -l"./configPkg/linker.cmd" "./tstgmp.obj" "./tdusim.obj" -l"libc.a"

<Linking>

undefined first referenced

symbol in file

--------- ----------------

__addd ./tdusim.obj

__args_main C:\Program Files\Texas Instruments\xdctools_3_20_07_86\packages\ti\targets\rts5500\lib\boot.a55L<boot_cg.o55L>

__cmpd ./tdusim.obj

__divd ./tdusim.obj

__fixdi ./tdusim.obj

__fltid ./tdusim.obj

__ftable ./tdusim.obj

__subd ./tdusim.obj

_exit C:\Program Files\Texas Instruments\xdctools_3_20_07_86\packages\ti\targets\rts5500\lib\boot.a55L<boot_cg.o55L>

_fclose ./tdusim.obj

_fflush ./tdusim.obj

_fopen ./tdusim.obj

_fprintf ./tdusim.obj

_fread ./tdusim.obj

_fseek ./tdusim.obj

_malloc ./tdusim.obj

_memcpy ./tstgmp.obj

_memset ./tdusim.obj

_muaTblAlaw ./tdusim.obj

_muaTblUlaw ./tdusim.obj

_pow ./tdusim.obj

_printf ./tdusim.obj

_sgnControl ./tdusim.obj

_sgnGenerateFrame ./tdusim.obj

_sgnGetSizes ./tdusim.obj

_sgnInit ./tdusim.obj

_sprintf ./tdusim.obj

_strcat ./tdusim.obj

_strcpy ./tdusim.obj

_tduControl ./tdusim.obj

_tduGetSizes ./tdusim.obj

_tduIncB202_MARKS_F ./tdusim.obj

_tduIncB202_SPACES_F ./tdusim.obj

_tduIncBELLRX1_T ./tdusim.obj

_tduIncBELLRX2_T ./tdusim.obj

_tduIncBELLTX1_F ./tdusim.obj

_tduIncBELLTX2_F ./tdusim.obj

_tduIncCNG_F ./tdusim.obj

_tduIncCPT ./tdusim.obj

_tduIncDTMF ./tdusim.obj

_tduIncR1 ./tdusim.obj

_tduIncR2BW ./tdusim.obj

_tduIncR2FW ./tdusim.obj

_tduIncSFDT_DUMMY1_T ./tdusim.obj

_tduIncSFDT_DUMMY2_T ./tdusim.obj

_tduIncSF_F ./tdusim.obj

_tduIncSS7COR_F ./tdusim.obj

_tduIncSS7COT_F ./tdusim.obj

_tduIncSS7COT_T ./tdusim.obj

_tduIncTT1khz_F ./tdusim.obj

_tduIncV18A_F ./tdusim.obj

_tduIncV18A_S_F ./tdusim.obj

_tduIncV21 ./tdusim.obj

_tduIncV21LOW_MARKS_F ./tdusim.obj

_tduIncV21LOW_SPACES_F ./tdusim.obj

_tduIncV21UPPER_MARKS_F ./tdusim.obj

_tduIncV23BW_MARKS_F ./tdusim.obj

_tduIncV23FW_MARKS_F ./tdusim.obj

_tduIncV23FW_MARKS_T ./tdusim.obj

_tduIncV25_F ./tdusim.obj

_tduIncV25_T_RX ./tdusim.obj

_tduIncV8BIS_FS_F ./tdusim.obj

_tduNew ./tdusim.obj

_tduOpen ./tdusim.obj

_tduReceiveIn ./tdusim.obj

_tduSendIn ./tdusim.obj

I am trying to implement the VOLIB libraries.  Is there maybe someone who is willing to share a CCS3 project?

Rob,

Attached is the new TDU and TDU test packages inside VoLIB, which contains CCS 4 test project for both big endian and little endian. Please let us know if it works for you, sorry for the delay. 

Regards, Eric

Instructions:

1)       Unzip the attached files to “…\volib_C64P_1_0_0_1\packages” folder.

2)       The CCS projects for TDU test can be located at:

Location:      “…\volib_C64P_1_0_0_1\packages\ti\mas\tdu\test”

Project Names: test_rel_c6482_C64PBE_BE_COFF and test_rel_c6482_C64PLE_LE_COFF

2654.ti_mas_tdu_obj_c64Px_2_3_0_0_beta.zip 

7571.ti_mas_tdu_src_c64Px_2_3_0_0_test.zip

Thanks. I was able to get the BE project imported and able to build, but only after changing the code generation tools to the version I have.

I'm not sure how I'm suppose to use these C64 files to compile for the C5505, my target of choice.

Thanks
Rob

Hi Eric

Thanks, got it working.

Regards

Maarten

Hi Eric

You guys don't have an example for the VAU unit by any change?

Maarten,

Below is a VAU project on C55x, CCS 3.3. Note, when testing, please change the test vectors relative path in test.c as below:

  if ((siuInst.inFrameFilePtr = fopen("..\\..\\test\\vectors\\inp\\in.raw", "rb")) == NULL) {
    printf(" Error opening in.raw\n");
    exit(0);
  }

  if ((siuInst.outFrameFilePtr =
    fopen("..\\..\\test\\vectors\\out\\out.raw", "wb")) == NULL) {
    printf(" Error opening out.raw\n");
    exit(0);
  }

Regards, Eric

=================================================

; Code Composer Project File, Version 2.0 (do not modify or remove this line)

[Project Settings]
ProjectDir="C:\DATA\Volib\volib_C55_1_0_0_1\packages\ti\mas\vau\vau_sim_c55x_ccs33\"
ProjectType=Executable
CPUFamily=TMS320C55XX
Tool="Compiler"
Tool="CustomBuilder"
Tool="DspBiosBuilder"
Tool="Linker"
Config="Debug"
Config="Release"

[Source Files]
Source="..\..\..\..\..\..\..\..\CCStudio_v3.3\C5500\cgtools\lib\rts55x.lib"
Source="..\test\src\mem.c"
Source="..\test\src\test.c"
Source="..\test\lnkr\c55l\test_rel_C5510.cmd"

["Compiler" Settings: "Debug"]
Options=-g -fr"$(Proj_dir)\Debug" -i"$(Proj_dir)\..\..\..\..\" -i"$(Proj_dir)\..\..\..\..\..\..\..\..\tools\gen\xdc\xdc_3_00_04\packages\" -i"$(Proj_dir)\..\..\..\..\..\..\..\..\tools\Xdais\xdais_5_21\packages" -d"_DEBUG" -d"ti_targets_C55_large" -d"xdc_target_types__=ti/targets/std.h" -ml

["Compiler" Settings: "Release"]
Options=-o2 -fr"$(Proj_dir)\Release"

["Linker" Settings: "Debug"]
Options=-c -m".\Debug\vau_sim_c55x_ccs33.map" -o".\Debug\vau_sim_c55x_ccs33.out" -w -x

["Linker" Settings: "Release"]
Options=-c -m".\Release\vau_sim_c55x_ccs33.map" -o".\Release\vau_sim_c55x_ccs33.out" -w -x

["..\test\lnkr\c55l\test_rel_C5510.cmd" Settings: "Debug"]
LinkOrder=1

["..\test\lnkr\c55l\test_rel_C5510.cmd" Settings: "Release"]
LinkOrder=1

Rob,

Attached is the new TDU and TDU test packages inside VoLIB, which contains CCS 4 test project for C55x target. 

Regards, Eric

Instructions:

1)       Unzip the attached 2 files to “…\volib_C55_1_0_0_1\packages” folder.

      2)       The CCS projects for TDU test can be located at:

Location:      “…\volib_C55_1_0_0_1\packages\ti\mas\tdu\test”

Project Name: test_rel_C5510_C55L_COFF

The Codegen version used for CCSV4 project is 4.3.5.

5808.ti_mas_tdu_obj_c55l_2_3_0_0_beta.zip

8715.ti_mas_tdu_src_c55l_2_3_0_0_test.zip

The same for the VAU would be nice too.

Thank
Rob

I was able to create a CCS4.0 project for the VAU using the TDU project as a sample. However the VAU requires XDCTools, forcing it to be an  RTSC enabled project.

After
0) creating a new CCS4 project in VAU/test, like the one in TDU/test,
1) creating a RTSC cfg file,
2) added C55 VoLIB packages folder to C/C++ Build Tool Settings XDC Tools Package Repositories RTCS package repositories (--xdcpath),
3) setting the Runtime Support Library to rts55x.lib in the CCS BUILD General panel,
4) checked only C55 VoLIB 1.0.0 and XDIAS 6.23 in the CCS BUILD RSTS Products and Repositories panel,
5) set C/C++ Build Tool Settings C5500 Compiler Basic Options -v to cpu:2.1,
6) Exclude from Build the lnk.cmd file (I assume this favors the XDAS settings),
7) probably some other settings too,
I got it to compile and run! I got the same output as the included outValDecisions.txt!

However, I get 2 warnings from the linker that I have not figured out how to fix:

-----
<Linking>

warning: creating output section ".nonVolatileMemBufs" without a SECTIONS specification
warning: creating output section ".volatileMemBufs" without a SECTIONS specification
'Finished building target: test_rel_C5505_C55L_COFF.out'
-----

Thanks
Rob

Rob,

"Some of the tests create output, many do not, I assume this is typical." ===> Yes, this is expected. When the tone power level is too high or too low, it is not going to be detected.

"It seems that the off time and on times are not being reported correctly” ===> please elaborate

“Also the data type of the frame number makes it such that it will count up from -32767 after reaching 32768. It also stalls for a time at -21199 at about 3/4 of the way through the tests."

This is printed from:

tuint frm_count; /* Count of frames generated */

You may change the print from %d to %u as below:

/* Print results to STDOUT and report file */

if (tduSim.options.add_tag) {

fprintf (stdout, "\n%s: %s, Time: %4d ms, Power: %3d dBm0, Frame: %u, %s",

event_string, tdu_event[on], time, power_MF, tduSim.txSGN.frm_count,

tduTestCaseTag);

fprintf (freport, "\n%s: %s, Time: %4d ms, Power: %3d dBm0, Frame: %u, %s",

event_string, tdu_event[on], time, power_MF, tduSim.txSGN.frm_count,

tduTestCaseTag);

}

else {

fprintf (stdout, "\n%s: %s, Time: %4d ms, Power: %3d dBm0, Frame: %u",

event_string, tdu_event[on], time, power_MF, tduSim.txSGN.frm_count);

fprintf (freport, "\n%s: %s, Time: %4d ms, Power: %3d dBm0, Frame: %u",

event_string, tdu_event[on], time, power_MF, tduSim.txSGN.frm_count);

}

fflush (stdout);

Hi Eric

Is it possible to use a different sample frequency other than 8 KHz or 16 KHz  for the VAU unit? We are currently using 20.833 KHz. Will I have to resample or is there maybe a way to change it?

Regards

Hi Eric

Could I reduce my sampling rate to 20833 / 3 and run the vau in 8 KHz mode?

Regards

Maarten,

VAU currently only supports 8K and 16K sampling rate. If your signal is 20.833K, your framework needs a down-sampler to do that. I am checking if you can use rate of 20.833/3 running at 8KHz mode.

Regards, Eric

Maarten,

The VAU algorithm is energy based by calculating a fixed block size of PCM input, the algorithm was developed for typical voice communication system at 8 KHz and 16 KHz rates.

If you use 20.833/3 = 6.94 KHz input and configure VAU in 8 KHz mode, it could work but this is not supported and tested by us.

Regards, Eric 

Hi Eric

The VAU algorithm works with a signal sampled at 6.94 KHz. I used male and female signals and seems to be ok. But when I add a relative big white noise component to any voice signal it seems not work that well. I would like to try the other simple voice activity detector in the VPE module.  Do you maybe have a sample project for me?

Regards

Hi Eric

Thanks a lot!

Regards

Maarten,

If there is no further questions, can you help to close this posting by click the green button "Verify Answer"  located at the lower right corner?

Regards, Eric

Hi Eric

I don't have the verify button on my screen, but it seems that it is verified.

Regards

Eric, I too do not see a button to "verify" that this thread is answered.

I can say that the sample configurations and buddy drop archive updates in this thread helped me create CCSV4.2.1 projects that build and execute code on a ezdsp5505 for the tdu, vau and vpe components of the VoLIB C55x 1.0.0 distribution.

Mission accomplished

Thanks, Rob

Maarten,

Thanks for letting me know. Yes, it is verified already some how.

Regards, Eric

Rob,

Glad to know everything worked fine! This post appeared to be verified already.

Regards, Eric

Hi All...

I have an issue with Packet Loss Concealment Unit in the VoLib built for C55x and CCSv4.

I created a project and tried to build. The C sorce files in the PLC require std.h file that is in xdc folder. But at the same time the std.h file require a select.h file that is in targets folder. When I include both these paths in the project build properties, then I get an error saying the some of the variables are already defined in this scope. This is because there is one more std.h in targets folder.

How to overcome this issue..?

Ashok,
this is an old thread that may not be really related to your problem. Can you start a new one and list the versions of XDCtools and SYS/BIOS you are using? Also, please post the complete error message you are using, as well the paths that you added to the project build properties?

Hi Sasha,

Thanks...

I have created a new thread and here is the link:

http://e2e.ti.com/support/dsp/c5000/f/109/p/357914/1256419.aspx#1256419