HOWTO Activate UART4 is AM35x_BSP ?

We have to use the UART4 device of the am3517.
Out basic BSP is AM35x_BSP.

So we tried to modify it, but until now I does not work:

- in bsp_padcfg.h we have defined a new Group

  #define UART4_PADS \
    PAD_ENTRY(CCDC_FIELD,INPUT_DISABLED                                      |MUXMODE(2)) \
    PAD_ENTRY(CCDC_HD,   INPUT_DISABLED                                      |MUXMODE(2)) \
    PAD_ENTRY(CCDC_VD,   INPUT_ENABLED |PULL_RESISTOR_ENABLED|PULLUP_RESISTOR|MUXMODE(2)) \
    PAD_ENTRY(CCDC_WEN,  INPUT_ENABLED |PULL_RESISTOR_ENABLED|PULLUP_RESISTOR|MUXMODE(2))

- in bsp_padcfg.c we have added

  const PAD_INFO UART4Pads[] = {UART4_PADS END_OF_PAD_ARRAY};
and
  const PAD_INFO* BSPGetDevicePadInfo(OMAP_DEVICE device)
  { switch (device)
    { ...
      case OMAP_DEVICE_UART4:    return UART4Pads;
      ...

- in bsp_bootstubs.c we have added ( as UART4 is a core-device, like UART1 and 2 )

  BOOL EnableDeviceClocks(UINT devId,BOOL bEnable)
  { OMAP_CM_REGS* pCmRegs;
    switch (devId)
    { ...
      case OMAP_DEVICE_UART4:
        pCmRegs = OALPAtoUA(OMAP_PRCM_CORE_CM_REGS_PA);
        if (bEnable)
        { SETREG32(&pCmRegs->CM_FCLKEN1_xxx,CM_CLKEN_UART4);
          SETREG32(&pCmRegs->CM_ICLKEN1_xxx,CM_CLKEN_UART4);
          while (INREG32(&pCmRegs->CM_IDLEST1_xxx) & CM_IDLEST_ST_UART4);
        }
        else
        { CLRREG32(&pCmRegs->CM_FCLKEN1_xxx,CM_CLKEN_UART4);
          CLRREG32(&pCmRegs->CM_ICLKEN1_xxx,CM_CLKEN_UART4);
        }
        break;
      ...

- in EBOOT\main.c we have added

  static VOID OEMPlatformDeinit()
  { ...
    EnableDeviceClocks(OMAP_DEVICE_UART4,FALSE);

- in oem_latency.c we have added

  BOOL OALWakeupLatency_DeviceEnabled( DWORD devId, BOOL bEnabled )
  { switch (devId)
    { ...
      case OMAP_DEVICE_EFUSE:
      case OMAP_DEVICE_UART4:
        if (bEnabled == TRUE)
        { #ifdef DEBUG_PRCM_SUSPEND_RESUME
            DeviceEnabledCount[devId]++;
      #endif
          ++_coreDevice;
        ...

- in am3517_clocks.h we dont know what to do

  Here IT IS NOT CLEAR, WHERE TO INCLUDE "OMAP_DEVICE_UART4" in the OMAP_DEVICE_ID enum.
  We can not understand the comments like //---10--- if the enum value of that entry is 5.
  Further it's not clear for us, how the entries are sorted ( are they sorted? ).
  Please give us a hint for the right enum value for OMAP_DEVICE_UART4.

- in am3517_base_regs.h we have added

  #define OMAP_UART4_REGS_PA 0x4809E000

- in uart.reg we have have included

  IF BSP_OMAP_UART4
  [HKEY_LOCAL_MACHINE\Drivers\BuiltIn\UART4]
  ...
 "DeviceArrayIndex"=dword:4
 "Index"=dword:4
  ...
  "MemBase"=multi_sz:"4809E000"
  ...
  ENDIF

  all other entries are like for the uarts 1,2,3

- in our Catalog we have defined an entry

  <BspItemId>abc:xyz:omapuart4_abc</BspItemId>
and
  <Item Id="abc:xyz:omapuart4_abc">
    <Title>UART4 driver</Title>
    <Description>Omap UART driver</Description>
    <Comment>Omap UART driver</Comment>
    <Type>BspSpecific</Type>
    <Variable>BSP_OMAP_UART4</Variable>
    <Variable>BSP_OMAP_GPIO</Variable>
    <Variable>BSP_OMAP_SDMA</Variable>
    <Module>omap_uart.dll</Module>
    <Location>Drivers\UART</Location>
  </Item>

- in our project we have added

  <Feature Name="Item" CatalogItemId="abc:xyz:omapuart4_abc" />

- in our platform.bib we have appended UART4:

  ; @CESYSGEN IF CE_MODULES_SERIAL
  #if (defined BSP_OMAP_UART1 || defined BSP_OMAP_UART2 || defined BSP_OMAP_UART3 || defined BSP_OMAP_UART4)
  omap_uart.dll       $(_FLATRELEASEDIR)\omap_uart.dll  NK  SHK
  #endif
  ; @CESYSGEN ENDIF CE_MODULES_SERIAL

Please assist us further with am3517_clocks.h.
Is there another place to pick into?

Best thanks
Hannes Brockmann

  • In PLATFORM\COMMON\SRC\SOC\COMMON_TI_V1\AM3517\SOCCFG\soccfg.c:

    You should add an entry for UART4 in the "SOCGetUartDeviceByIndex" function.

    In PLATFORM\COMMON\SRC\SOC\COMMON_TI_V1\AM3517\SOCCFG\devicemap.c:

    You should add an entry for linking OMAP_UART4_REGS_PA to OMAP_DEVICE_UART4 in the s_DeviceAddressMap structure, and an entry for the IRQ in the s_DeviceIrqMap structure.

    This should work better as the real link between the device ID and the registers base address is done using soccfg and devicemap and no through the "membase"' registry key as you were probably expecting. If it still does not work, please post some log of the failures you get when initializing the UART4 driver.

  • Also, concerning am3517_clocks.h, you could add an entry pretty much anywhere you want, as long as OMAP_DEVICE_SGX does not move (hard-coded in POWERVR libraries). I'd advise you to replace insert it after OMAP_DEVICE_HDQ and delete OMAP_DEVICE_STUB3 to preserve the POWERVR library. Comments would also need to be shifted if you want to stay coherent.

    You finally need to add a clock entry in prcm_device.h structure s_rgDeviceLookupTable, order has to follow order defined in am3517_clocks.h:

        }, {
            POWERDOMAIN_CORE,                 // OMAP_DEVICE_UART4
            &_fclk_UART4,   
            &_iclk_UART4,
            NULL,
            &_idleStat_UART4,     
            &_autoIdle_UART4,
            &_CORE_48M_SourceClock,
        }, {

    And even though the datasheet we have is not consistent in whether the FCLK for UART4 can be enabled or not, you should probably add the missing following line

    FCLK_DECL(_fclk_UART4, 0, CM_CLKEN_UART4, cm_offset(CM_FCLKEN1_xxx));

    AUTOIDLE_DECL(_autoIdle_UART4,  FALSE,   CM_CLKEN_UART4,    cm_offset(CM_AUTOIDLE1_xxx));

    After you have done all that, make you sure you rebuild the BSP entirely to make sure you propagate those deep changes to all the drivers.

  • In reply to Adeneo Embedded support team:

    Hello and thanks for Your answers.

    We have done all changes for UART4 activation.

    In prcm_device.h we had to use &_48M_Source_Clock instead of &_CORE_48M_Source_Clock, because it was'nt there.

    Additional we have added an entry for UART4 in the DEVICE_OPP_TABLE in devoppmap.h:

    DECL_DEVICE_OPP_MAP(OMAP_DEVICE_UART4, D4, kOpm0, POWERDOMAIN_CORE),\

    After that we have cleaned and rebuild the entire BSP.

    Now the system is booting ... until

    Windows CE Kernel for ARM (Thumb Enabled)
    INFO:OALLogSetZones: dpCurSettings.ulZoneMask: 0x800f
    +OEMInit
    +OALPowerInit()
     Disable serial debug messages during PRCM DeviceInitialize
     Serial debug messages renabled
    -OALPowerInit()

    and than hangs up.

    What would be the suggested way to get out of that?

    How can one debug further?

    Best thanks

    Hannes Brockmann

     

  • In reply to Hannes Brockmann:

    Hello once more

    I now have stepped along the code including temporary RETAILMSGes:

    ... runs into OALIntrInit() in \platform\common\src\soc\COMMON_TI_V1\COMMON_TI\OAL\OMAP_INTR\intr.c.

    ... here it stocks ( I dont know why? ):

    RETAILMSG(1,(L"OALIntrInit s_intr.nbGpioBank=%d\r\n",s_intr.nbGpioBank));
    for (i=0;i<s_intr.nbGpioBank;i++)
    { RETAILMSG(1,(L"OALIntrInit start loop=%d\r\n",i));
      //Disable interrupt/wakeup
      OUTREG32(&s_intr.pGpioCtxt[i].pRegs->IRQENABLE1, 0x00000000);
    ==> THIS POINT IST NEVER REACHED ALREADY IN THE FIRST LOOP  
      RETAILMSG(1,(L"OALIntrInit 1 loop=%d\r\n",i));
      ...       
      RETAILMSG(1,(L"OALIntrInit end loop=%d\r\n",i));
    }

    here is the log:

    Windows CE Kernel for ARM (Thumb Enabled)
    INFO:OALLogSetZones: dpCurSettings.ulZoneMask: 0x800f
    +OEMInit
    +OALPowerInit()
     Disable serial debug messages during PRCM DeviceInitialize
     Serial debug messages renabled
    -OALPowerInit()
    INFO: OEMInit: before VfpOemInit
    INFO: OEMInit: behind VfpOemInit
    INFO: OEMInit: before OALIntrInit
    OALIntrInit s_intr.nbGpioBank=6
    OALIntrInit start loop=0

    please help.

    Thanks. Hannes Brockmann

  • In reply to Hannes Brockmann:

    Hello!

    what success with the launch of UART4 on these  pins?

    i also need this UART4 on camera pins.

    currenly i stucked on this code.

    in function

    static VOID InitializeUART(UARTPDD *pPdd)

    //================

        // Reset UART & wait until it completes
        OUTREG8(&pUartRegs->SYSC, UART_SYSC_RST);
        
        DEBUGMSG(ZONE_FUNCTION, (TEXT("+InitializeUART 0 \r\n")));                        
        
        while ((INREG8(&pUartRegs->SYSS) & UART_SYSS_RST_DONE) == 0);

        DEBUGMSG(ZONE_FUNCTION, (TEXT("InitializeUART here 1\r\n")));    
    //=============

    in debug i have this output:

    PID:00400002 TID:014E000A About to call HWInit(Drivers\Active\4294967291,0xCC888D60)
    PID:00400002 TID:014E000A +HWInit(Drivers\Active\4294967291, 0xcc888d60, 0xc44511b0
    PID:00400002 TID:014E000A
    HWInit: MmMapIoSpace: 0x00000000
    PID:00400002 TID:014E000A HWInit: pPdd->UARTIndex: 0x00000004
    PID:00400002 TID:014E000A HWInit: pPdd->memBase[0]: 0x4809e000
    PID:00400002 TID:014E000A HWInit: pPdd->irq: 0x00000054
    PID:00400002 TID:014E000A HWInit: pPdd->pUartRegs 0xccce0000
    PID:00400002 TID:014E000A HWInit: TxDmaRequest= -1
                                                      PID:00400002 TID:014E000A HWInit: RxDmaRequest= 50

    PID:00400002 TID:014E000A OMAP35XX RX DMA buffer allocated
                                                              PID:00400002 TID:014E000A  steep1
    PID:00400002 TID:014E000A UART:SetPower: D0 (curDx=D4)
    PID:00400002 TID:014E000A here5
    PID:00400002 TID:014E000A here6
    PID:00400002 TID:014E000A here7
    PID:00400002 TID:014E000A UART: -SetPower Device Power state D0
    PID:00400002 TID:014E000A  steep2
    PID:00400002 TID:014E000A  steep3
    PID:00400002 TID:014E000A +InitializeUART INREG8(&pUartRegs->SYSC) = 0
    PID:00400002 TID:014E000A +InitializeUART INREG8(&pUartRegs->SYSS) = 1
    PID:00400002 TID:014E000A CONTROL_PADCONF_MCBSP3_FSX  uart2_rx   (0xccd50172) 0x119
    PID:00400002 TID:014E000A CONTROL_PADCONF_MCBSP3_CLKX uart2_tx     (0xccd50170) 0x1
    PID:00400002 TID:014E000A CONTROL_PADCONF_MCBSP3_DR   uart2_rts     (0xccd5016e) 0x1
    PID:00400002 TID:014E000A CONTROL_PADCONF_MCBSP3_DX   uart2_cts     (0xccd5016c) 0x119
    PID:00400002 TID:014E000A CONTROL_PADCONF_UART2_CTS       (0xccd50174) 0x107
    PID:00400002 TID:014E000A CONTROL_PADCONF_UART2_RTS        (0xccd50176) 0x107
    PID:00400002 TID:014E000A CONTROL_PADCONF_UART2_TX        (0xccd50178) 0x107
    PID:00400002 TID:014E000A CONTROL_PADCONF_UART2_RX        (0xccd5017a) 0x107
    PID:00400002 TID:014E000A CONTROL_PADCONF_CCDC_FIELD        (0xccd501e6) 0x2
    PID:00400002 TID:014E000A CONTROL_PADCONF_CCDC_HD      (0xccd501e8) 0x2
    PID:00400002 TID:014E000A CONTROL_PADCONF_CCDC_VD       (0xccd501ea) 0x11a
    PID:00400002 TID:014E000A CONTROL_PADCONF_CCDC_WEN        (0xccd501ec) 0x11a
    PID:00400002 TID:014E000A CM_ICLKEN1_CORE          (0xccd30a10) 0x80004a
    PID:00400002 TID:014E000A CM_FCLKEN1_CORE          (0xccd30a00) 0x800000
    PID:00400002 TID:014E000A CM_IDLEST1_CORE          (0xccd30a20) 0xff7fffbd
    PID:00400002 TID:014E000A CM_AUTOIDLE1_CORE          (0xccd30a30) 0x7ffffed1
    PID:00400002 TID:014E000A CM_FCLKEN_PER          (0xccd20000) 0x3e808
    PID:00400002 TID:014E000A CM_ICLKEN_PER          (0xccd20010) 0x3e808
    PID:00400002 TID:014E000A CM_IDLEST_PER          (0xccd20020) 0x17f7
    PID:00400002 TID:014E000A CM_AUTOIDLE_PER        (0xccd20030) 0x3ffff
    PID:00400002 TID:014E000A pGpio_reg->OE          (0xccd60034) 0xffffffff

    PID:00400002 TID:014E000A pGpio_reg->DATAIN          (0xccd60038) 0x800

    PID:00400002 TID:014E000A pGpio_reg->WAKEUPENABLE          (0xccd60020) 0x0

    PID:00400002 TID:014E000A pGpio_reg->DEBOUNCENABLE          (0xccd60050) 0x0

    PID:00400002 TID:014E000A pGpio_reg->DEBOUNCINGTIME          (0xccd60054) 0x0

    PID:00400002 TID:014E000A pGpio_reg->SYSCONFIG          (0xccd60010) 0x15

    PID:00400002 TID:014E000A pGpio_reg->REVISION          (0xccd60000) 0x25

    PID:00400002 TID:014E000A pGpio_reg->CTRL          (0xccd60030) 0x2

    PID:00400002 TID:014E000A +InitializeUART 0

    and we sit here for infinity -(

    Why UART4 not come back from soft reset?

  • In reply to Andrew Efremov:

    It really looks like your UART4 controller clocks are not enabled, which produces crashes when accessing its registers. Please double check that those are enabled by using the debugging inside the "PrcmDeviceEnableFClock" and "PrcmDeviceEnableIClock" functions located under :WINCEROOT\PLATFORM\COMMON\SRC\SOC\COMMON_TI_V1\OMAP3530\OAL\PRCM\prcm_device.c.

    At initialization, those functions should be called with "devId" being the device ID defined for OMAP_DEVICE_UART4 as described in our first replies to this post.

  • In reply to Adeneo Embedded support team:

    Functional and  interface clock are enabled.

    i put debug code like this in static VOID InitializeUART(UARTPDD *pPdd)

    static VOID InitializeUART(UARTPDD *pPdd)
    {
        OMAP_UART_REGS *pUartRegs = pPdd->pUartRegs;

        DEBUGMSG(ZONE_FUNCTION, (TEXT("+InitializeUART INREG8(&pUartRegs->SYSC) = %x\r\n"),INREG8(&pUartRegs->SYSC)));                        
            DEBUGMSG(ZONE_FUNCTION, (TEXT("+InitializeUART INREG8(&pUartRegs->SYSS) = %x\r\n"),INREG8(&pUartRegs->SYSS)));                        


    //======================= debug EAI
    {
        
        PHYSICAL_ADDRESS pa;
        static OMAP_PRCM_CORE_CM_REGS           *pOMAP_PRCM_CORE_CM_REGS;
        static OMAP_PRCM_CLOCK_CONTROL_CM_REGS  *pOMAP_PRCM_CLOCK_CONTROL_CM_REGS;
        static OMAP_SYSC_PADCONFS_REGS          *pConfig;
        static OMAP_GPIO_REGS     *pGpio_reg;
        static OMAP_PRCM_PER_CM_REGS     *pPCRM_PER_reg;

        

        pa.QuadPart      = OMAP_PRCM_PER_CM_REGS_PA;
        pPCRM_PER_reg = (OMAP_PRCM_PER_CM_REGS *)MmMapIoSpace(pa, sizeof(OMAP_PRCM_PER_CM_REGS), FALSE);


        pa.QuadPart      = OMAP_PRCM_CORE_CM_REGS_PA;
        pOMAP_PRCM_CORE_CM_REGS = (OMAP_PRCM_CORE_CM_REGS *)MmMapIoSpace(pa, sizeof(OMAP_PRCM_CORE_CM_REGS), FALSE);

        pa.QuadPart      = OMAP_PRCM_CLOCK_CONTROL_CM_REGS_PA;
        pOMAP_PRCM_CLOCK_CONTROL_CM_REGS = (OMAP_PRCM_CLOCK_CONTROL_CM_REGS*)MmMapIoSpace(pa, sizeof(OMAP_PRCM_CLOCK_CONTROL_CM_REGS), FALSE);

        pa.QuadPart   = OMAP_SYSC_PADCONFS_REGS_PA;
        pConfig       = (OMAP_SYSC_PADCONFS_REGS *)MmMapIoSpace(pa, sizeof(OMAP_SYSC_PADCONFS_REGS), FALSE);

        pa.QuadPart       = OMAP_GPIO5_REGS_PA;
        pGpio_reg           = (OMAP_GPIO_REGS *)MmMapIoSpace(pa, sizeof(OMAP_GPIO_REGS), FALSE);



    //
        RETAILMSG(1,(TEXT("CONTROL_PADCONF_CCDC_FIELD        (0x%x) 0x%x\r\n"),&pConfig->CONTROL_PADCONF_CCDC_FIELD,  pConfig->CONTROL_PADCONF_CCDC_FIELD  ));
        RETAILMSG(1,(TEXT("CONTROL_PADCONF_CCDC_HD      (0x%x) 0x%x\r\n"),&pConfig->CONTROL_PADCONF_CCDC_HD,pConfig->CONTROL_PADCONF_CCDC_HD));
        RETAILMSG(1,(TEXT("CONTROL_PADCONF_CCDC_VD       (0x%x) 0x%x\r\n"),&pConfig->CONTROL_PADCONF_CCDC_VD, pConfig->CONTROL_PADCONF_CCDC_VD ));
        RETAILMSG(1,(TEXT("CONTROL_PADCONF_CCDC_WEN        (0x%x) 0x%x\r\n"),&pConfig->CONTROL_PADCONF_CCDC_WEN,  pConfig->CONTROL_PADCONF_CCDC_WEN  ));
    //
    //
        RETAILMSG(1,(TEXT("CM_ICLKEN1_CORE          (0x%x) 0x%x\r\n"),&pOMAP_PRCM_CORE_CM_REGS->CM_ICLKEN1_CORE,   pOMAP_PRCM_CORE_CM_REGS->CM_ICLKEN1_CORE ));
        RETAILMSG(1,(TEXT("CM_FCLKEN1_CORE          (0x%x) 0x%x\r\n"),&pOMAP_PRCM_CORE_CM_REGS->CM_FCLKEN1_CORE,   pOMAP_PRCM_CORE_CM_REGS->CM_FCLKEN1_CORE ));
        RETAILMSG(1,(TEXT("CM_IDLEST1_CORE          (0x%x) 0x%x\r\n"),&pOMAP_PRCM_CORE_CM_REGS->CM_IDLEST1_CORE,   pOMAP_PRCM_CORE_CM_REGS->CM_IDLEST1_CORE ));
        RETAILMSG(1,(TEXT("CM_AUTOIDLE1_CORE          (0x%x) 0x%x\r\n"),&pOMAP_PRCM_CORE_CM_REGS->CM_AUTOIDLE1_CORE,   pOMAP_PRCM_CORE_CM_REGS->CM_AUTOIDLE1_CORE ));

        RETAILMSG(1,(TEXT("CM_FCLKEN_PER          (0x%x) 0x%x\r\n"),&pPCRM_PER_reg->CM_FCLKEN_PER,   pPCRM_PER_reg->CM_FCLKEN_PER ));
        RETAILMSG(1,(TEXT("CM_ICLKEN_PER          (0x%x) 0x%x\r\n"),&pPCRM_PER_reg->CM_ICLKEN_PER,   pPCRM_PER_reg->CM_ICLKEN_PER ));
        RETAILMSG(1,(TEXT("CM_IDLEST_PER          (0x%x) 0x%x\r\n"),&pPCRM_PER_reg->CM_IDLEST_PER,   pPCRM_PER_reg->CM_IDLEST_PER ));
        RETAILMSG(1,(TEXT("CM_AUTOIDLE_PER        (0x%x) 0x%x\r\n"),&pPCRM_PER_reg->CM_AUTOIDLE_PER,   pPCRM_PER_reg->CM_AUTOIDLE_PER ));

    and i have this in debug terminal

    PID:00400002 TID:014E000A CONTROL_PADCONF_CCDC_FIELD        (0xccd501e6) 0x2
    PID:00400002 TID:014E000A CONTROL_PADCONF_CCDC_HD      (0xccd501e8) 0x2
    PID:00400002 TID:014E000A CONTROL_PADCONF_CCDC_VD       (0xccd501ea) 0x11a
    PID:00400002 TID:014E000A CONTROL_PADCONF_CCDC_WEN        (0xccd501ec) 0x11a
    PID:00400002 TID:014E000A CM_ICLKEN1_CORE          (0xccd30a10) 0x80004a                                  <------------------------------- bit 23 enable clock
    PID:00400002 TID:014E000A CM_FCLKEN1_CORE          (0xccd30a00) 0x800000                                 <------------------------------- bit 23 enable clock
    PID:00400002 TID:014E000A CM_IDLEST1_CORE          (0xccd30a20) 0xff7fffbd
    PID:00400002 TID:014E000A CM_AUTOIDLE1_CORE          (0xccd30a30) 0x7ffffed1
    PID:00400002 TID:014E000A CM_FCLKEN_PER          (0xccd20000) 0x3e808
    PID:00400002 TID:014E000A CM_ICLKEN_PER          (0xccd20010) 0x3e808
    PID:00400002 TID:014E000A CM_IDLEST_PER          (0xccd20020) 0x17f7
    PID:00400002 TID:014E000A CM_AUTOIDLE_PER        (0xccd20030) 0x3ffff

    I see strange behavior:

    if i use power management  minimal (SYSGEN_PMSTUBS)  we stuck then initialize UART4, but not stuck on others UARTs (UART1 and UART2 works fine)

    if i use power management full (SYSGEN_PM) we dont stuck on initialization of UART4 and others.

    I understand that I need to turn on something in control REGs. but what ?

  • In reply to Andrew Efremov:

    The power management framework is mandatory as it is needed for the custom OMAP bus driver to work well (PLATFORM\COMMON\SRC\SOC\COMMON_TI_V1\COMMON_TI\BUS). This bus driver replaces the regular "Builtin" bus and correctly initializes all controllers (clocks, power, etc..) when corresponding drivers are loaded.

  • In reply to Adeneo Embedded support team:

     But can someone tell which bits in the control registers of AM3517 must be set for not stuck in UART reset.

    f and i clocks are enabled:

     CM_ICLKEN1_CORE    =       0x80004a                          here bit 23 are set
     CM_FCLKEN1_CORE   =       0x800000                        and here this bit set

    CM_IDLEST1_CORE        = 0xff7fffbd  here bit 23 = 0x0: UART4 can be accessed.

    what any more this UART need for not stuck then we make soft reset by writing in SYSC

    OUTREG8(&pUartRegs->SYSC, UART_SYSC_RST);

    may be ask an TI engineer who knows the hardware of AM317 very good.