I have a custom assembly, with version 2.1 silicon, -4 parts; 64 MB DDR2 .All is working fine at 300 MHz, with the platform booting from SPI1 and SD card.I have run CCS5 applications to test the hardware at 456MHz with no problems.In order to get our WinCE platform up to 456 MHz, I have done the following:1. Using the SFH 2.36 code, edited the device.c file (and the UART file) to produce a SPI UBL that boots at 456 MHz. (Using the OMAPL138_LCDK device).2. Edited the BSP catalog file, to add a radio button selection for OMAP-L138 456, which sets SOC_OMAPL138 and SOC_CLOCK456.3. Cleaned/built Release, to produce an EBOOTSPIFLASH.nb0.
4. Used CCS5 and SpiWriterARM to burn the UBL and EBOOTSPIFLASH (as I did for 300 MHz.)
While the UBL starts fine, at 'Jumping to 0xC3F60000', there appears to be either a prefetch or data abort( snooping with CCS5 ). If I burn the 300MHz UBL, keeping the 456 EBOOT, the UBL debug output is fine,but of course once EBOOT runs the baud rate shifts and corrupt debug stream goes to UART.I have also tried AISGen on the EBOOT file, and it does configure clock and DDR correctly, loadsEBOOT, but hits a data abort in KernelRelocate() in startup.Am I missing a step here? Another define or Env Var? .... Is there any plan to support the LCDK in the BSP?Thanks! -- Joe
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