TI E2E Community
NAND Isuue - Number Of Partial Pages
My customer is using AM37303 with WINCE 6 OS and Micron NAND 4-bits ECC MT29F4G16ABBDAHC-IT.
After testing the device with Stress tests of reading and writing random files to the file system it looks that there are problems:
After a lot of investigations, a critical issue was raised:
There is a different between the number of partial pages which required by the Partition manager In WINCE when the wear leveling feature is enable(5 NOP) and
between the max number of partial pages which defined in the Nand datasheet.
During continues investigation I see that lot of the problem isn’t in an error correction method but it is in a corruption of the spare are.
If the spare area doesn’t covered by ECC, the invalid information about page will pass to the wear leveling part of the FSD. It means that storage may be destructed completely because the corruption the single page’s spare area.
I believe that the spare area’s guarding by ECC may solve the problem. How to do this?
Currently we use the wrapping mode 6 for read and mode 9 for write. It means that ECC engine is inactive during spare are read/write.
We must to choose the different wrapping mode to cover the spare area by ECC. (7 for write and 3 for read or something like)
Here we have some trebles.
Is it possible?
Can you to direct us to right source?
Can you please advice on his questions?
Can someone answer the questions above?
See reply on double post: http://e2e.ti.com/support/embedded/wince/f/353/t/180314.aspx
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