Part Number: TPD5S115
Test conditions: I2C speed of 400KHZ.Pull the A-side HPD_A up to 1.8V and the handset AP sends an I2C instruction to test the SCL_A / SDA_A / SCL_B / SDA_B-side waveform (B-side HDMI terminal is floating and not connected).The problem is:1. SCL_B is delayed by about 800 ns compared to the falling edge of SCL_A. (Refer to 1.8v-5v-scl.bmp)
2, SDA_B is delayed by about 350ns compared to SDA_A falling edge. (Refer to 1.8v-5v-sda.bmp)
While the normal value of the specification value of 370ns, that is, SDA is in line with the specifications of the book, but the SCL does not meet, and the difference is more.Because the delay of SCL will cause problems with B-side I2C timing. (Refer to 5v-scl-sda.bmp)
I apologize for my delay. I will study this and get back to you.
In reply to Cameron Phillips:
Have you checked this question? My customer has the same question now . Thank you .
In reply to qiang xiang:
The schematic of TPD5S115 is belows:
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.