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TPD5S116 Dip on SCL_CON, SDA_CON

Other Parts Discussed in Thread: TPD5S116

Hi Team,

Can you advise me on signal dip on SCL_CON, SDA_CON and CEC_CON.

When Sink device is connected and HPD_CON changed Low to High, SCL_CON, SDA_CON and CEC_CON
Showed dip about 400 ns after the HPD assertion with about 200 ns duration.


                                       _________________________
HPD _______________|

                                     ~400ns   ~200 ns
                     ________________     ________________
SCL_CON                                   |_/


Is this expected symptom?

I suspect that the Level shifter block in the device may influence to this symptom.
I wonder if you can explain me the behavior of this block?

Mita

  • Hi Team,

    Customer is using this device in their application. Could you please help us support them ?

    Best Regards,
    Kawai
  • Kawai and Mita-

    I'm working to understand this issue and will get back to you when I have an answer, hopefully in a few days. Thanks for your patience.

    Thanks,
    Alec
  • Hello Alec-san,

    Thank you for your support. We look forward to hearing from you.

    I am pasting waveform image since the one above were misaligned.

    Best Regards,

    Kawai

  • Hello Alec-san,

    Do you have any update ? We need you support on this question.

    Thanks in advance.

    Best Regards,
    Kawai
  • Kawai-

    Looking closer at this, I'm not sure what this part could be doing to pull down the I2C lines, as it is just pass through with a few pull ups when the device is not enabled. 

    Would it be possible for you to get a measurement of both the system and connector side on SCL? It's possible that the drop is a signal being driven by your application, and that you only see it after HPD goes high because the level shifters in the TPD5S116 are disabled beforehand and the signal won't be measured on the connector side. As far as I can see, there is nothing inside of the TPD5S116 that should be driving the SCL signal low. To see a bit more information on the level shifter operation, it might be helpful to look at section 8.3.9 in the TPD5S116 datasheet.


    Thanks,

    Alec

  • Hello Alec-san,

    My apologies for my delay. I will let you know as soon as I obtain the waveform data.

    We greatly appreciate for your support.

    Best Regards,
    Kawai
  • Hello Alec-san,

    My apologies for my delay. We obtained the waveform data from customer. I would like to share the data with you. Could you please allow us to discuss offline ?

    I also found the following description in the datasheet. When HDP_CON is High and HPD_SYS is Low,  the device seems to pull down SCL. We could not observe this Low signal during this condition, however, we see this SCL dip after HPD_SYS is High.

    Why is this pull down function designed for ? It seems this function is relating to our customer problem.



    Best Regards,
    Kawai

  • Hello Team and Experts,

    Could you please help us support our customer ?
    We appreciate it if you could allow us to discuss offline, as we would like to share customer waveforms.

    Best Regards,
    Kawai
  • Hi Kawai-san,

    This issue is due to the power-up of these specific lines once the 5V HPD occurs. The delay is then caused by the glitch filter on the lines, which is why you see the 10ns delay after power-up.

    Glad I could help out.

    Very Respectfully,
    Brian Dempsey
  • Hello Brian-san,

    Thank you for your continuous support.
    We understood that this is normal operation for TPD5S116.

    Could you please change the status of this post to "ANSWERED" since I cannot verify your answer ?

    Best Regards,
    Kawai