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TPD4S014: Discrepancy between user guide and actual PCB

Part Number: TPD4S014

Hi,

I have several questions relating to the TPD4S014 and its EVM on behalf of an engineer.

1.The TPD4S14EVM that was received upon EVM-order match the picture on the product page at TI.com. However, the EVM layout in the user's guide does not correspond to the actual board (earlier revision?). That means that the schematics, enumeration etc are incorrect. Do you have updated schematics for the TIDAP-19912-02?

2. In the datasheet (p.17, section 10.2) there are recommendations for the layout. What is not commented is the connection of ground to the USB contact. What's your advice? Do you recommend to place a cap or coil between the ground and shield in the USB-cable and the chassi on the card? In the EVM user's guide, the schematic depicts connection between earth on the USB bus (J2/3:5) directly to the chassi (pin 8,9), whereas there is a decoupling cap of 10uF between VBUS and the chassi (pin 6,7). Is this the recommended layout? It is hard to say how the design of the actual EVM looks like without the schematics and how it relates to the design rules in the datasheet.

3. In the schematics to the EVM user's guide, there are two kinds of ceramic capacitors (C1 and C2). One kind on one side of the PCB and another kind on the other side of the TPD4S014. Is there a reason behind this? In particular, why does the cap rated for a lower voltage (C1) face the outer world?      

I appreciate your swift reply.

Thanks in advance,

Gustaf

  • Gustaf,

    I will have to do some research on your questions and get back to you. I will follow up as soon as possible.

    Regards,
    Chuck
  • Gustaf,

    I have done some further research:

    1. I reviewed the layout of the EVM and I do see that it uses the ID pin as a AC ground shield for the D+/D- lines between the two USB connectors which is not the most ideal configuration from an RF standpoint, but I would expect the resulting path to meet the USB 2.0 specifications because the ID line should be an AC equivalent ground. If your customer has the board area available, the ID line should be pulled away from the D+ line to allow for a top level PCB ground shield. This EVM does not have a MCU or other device that is being protected by the TPD4S014, so the design will be different.

    I do not have access to the EVM layout and schematic right now, but I am trying to get them.

    2. Most of the boards that I have seen place a choke between the chassis ground and the PCB ground to reduce EMI. This is perfectly acceptable as long as the protection device is placed close to the PCB side of the choke to reduce possible ground resistance within the ESD protection scheme.

    3. The voltage selection of C2 is most likely done because it is intended to be connected to the external USB port and will be subject to large transient signals that might cause a lower voltage rated capacitor to break down. C1 is supposed to be an internal capacitor that is not exposed to an external port with large possible transients, so it's voltage rating is much lower and it can be a smaller body size because of this. For this EVM, it probably should have been a 35V capacitor because it is connected to a USB connector, but I assume that the board designer wanted to represent a customer system and allow for the smaller body size.
  • Thanks Chuck! Please keep me updated if you get hold of the schematics.
    Kind regards,
    Gustaf
  • Hi Chuck,

    Have you been able to dig out a schematic?


    Kind regards,

    Gustaf