Hi team,
My customer has following questions.
Please let me know the answers.
①Is there a signal input sequence between CT_HPD and LS_OE?
If there is a signal input sequence, please let me know the order and time value.
②Do CT_HPD and LS_OE have rise/fall time specifications?
If they have, please let me know the values.
③I want to know a wait time from the time LS_OE and CT_HPD become high to the time I2C
communication is permitted.
④SCL_A and SDA_A pulled up to VccA in the datasheet Functional Block Diagram.
But I think SCL_A and SDA_A are pulled up to 3.3V(internal). Because SCL_A and SDA_A have
a certain delay from the time the power supply of the VCCA is turned on until they are pulled up.
Is this correct?
Best regards,
Fumio Nakano