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Is there really nobody out there who can answer my questions?

Hi Fred,

I was just made aware of your post 30mins ago.

I am the design lead for TUSB1210 and TUSB1211 products.

Yes this feature is admittedly poorly documented in the datasheet.

Please find the following information which should help you with your application:

SOF feature can be enabled by SOF_EN bit
SOF_EN is bit5 of VENDOR_SPECIFIC6 register (address offset 0x8E), default logic low (disabled)
Only HS SOF is supported, FS/LS SOF is not supported
HS USB SOF packet rate is 8 kHz.
SOF pin logic is CMOS-type on VDDIO (1.8V) supply
SOF’s generated only when PHY is in receive mode mode
SOF’s are disabled until a 1^st SOF PID has been detected
480MHz PHY clock is generated by internal PLL based on CLK (60MHz) in “input clock mode”, or REFCLK (19.2MHz / 26MHz) in “output clock mode”
Missing SOFs are inserted if the next SOF pulse is not received after 7503 cycles of 60MHz clock from PHY (which is 480MHz PHY clock divided-by-8)
• This is to ensure that a "missing SOF" is only ever inserted after 125us is guaranteed to have elapsed based on fastest possible clock 60MHz+500ppm.
• Note that if a missing SOF is inserted then SOF detection is ignored for the next five 60MHz clock cycles to ensure a double SOF is never generated    
Rising edge of SOF output clock signal is synchronized on 60MHz. This is the edge to be used by systems making use of TUSB1211 SOF pin.
Falling edge of SOF output clock is synchronized on internal CK32K such that minimum SOF “high” duration is 1 period of CK32K
SOF jitter corresponds to 60MHz and 480MHz jitter of 208.33ps max (see chapters 7.1.2.2 and 7.1.15.2 of USB2.0 specification) 
Delay from SOF packet to SOF pin rising edge is a fixed deterministic delay but I do not have this number today. We would need to check in simulation. 

Currently TUSB1211  full datasheet can be distributed only under NDA (Non Disclosure Agreement). I need to check if your company has one in place with TI? Could you please contact your local TI representative. Failing this please send an email to me at p-considine@ti.com and we can discuss your requirements further.

Looking at your specific Q's:

1. Is there a register description of the TUSB1211 available which would allow me to utilize the SOF output?

[Peter] Please see above.

2. Is there any timing information of the SOF output, e.g. jitter and delay between USB SOF and the signal appearing on the SOF pin F6 available?

[Peter] Please see above

3. What will the SOF pin do in case the TUSB1211 misses one or several Start Of Frames because of transmission errors?

[Peter] Please see above

4. If the TUSB1211 is configured to output a 60 MHz ULPI Clock signal on pin A4, is this clock in phase (locked) to the recovered 240 MHz HS-USB clock?

[Peter] Please see above. The SOF signal is synchronized with 60MHz clock. 60MHz clock is derived from internal 480MHz clock. The internal 480MHz PHY clock is not recovered from USB data. It is generated independently by the PHY but its phase is set in order to optimise data recovery, and its drift meets USB2.0 requirements (as described in HS eye diagram description of USB2.0 spec chapters 7.1.2.2 and 7.1.15.2 ) .  

5. What would be the expected jitter on the 60 MHz ULPI clock output?

[Peter] Please see above.

I hope I have answered most of your questions. Please contact me if you need further information.

Best regards,

Peter

Is there a good reference schematic for using this part in host only mode?   I'm assuming the default configuration (base on datasheet) is host mode.

Some background.....  We switched from this part SMSC USB3322 (Used on original beagleboards) to the TUSB1211.  Are there any key design differences that we should be aware of making that work with a OMAP.  We originally assumed it was a drop in, but it doesn't seem to be working (can't access registers over ULPI interface and no negotiation for devices that are plugged in).

I just noticed, that from the spec both CS pins maybe should be pulled up.  If you read about CS_N first, you would tie it to ground, but looking at CS, it notes that CS_N might be pulled high (or maybe low) when CS is high for normal operation. 

.

=> Regarding CS and CS_N please find bellow the way to use it:
- CS : Active-high chip select pin. When low the IC is in power down and ULPI bus is tri-stated. When CS is high (and CS_N pin is Tie to VDDIO if unused.s low) normal operation.
- CS_N : Active-low chip select pin. When high the IC is in power down and ULPI bus is tri-stated. When CS_N is low (and CS pin is high) normal operation. Tie to GND if unused.

Please refer to http://www.ti.com/product/tusb1211 document Table 2-1. Terminal Functions.

=> Please find bellow a reference schematic :
3542.TUSB1211 in ULPI output clock mode.pdf

=> Please find bellow a Basic low-level test to check TUSB1211 device is alive?
Otherwise if it is very low-level testing you are referring to then you should bias TUSB1211 as in the application diagrams shown in TUSB1211 spec:
-       Apply VBAT (2.7V ~ 4.8V)
-       Apply VDDIO (1.8V)
-       Check CS, RESETB pin levels are VDDIO, CS_N is at GND
-       Set REFCLK (output CLOCK mode), or CLOCK (input CLOCK mode).

• If output clock mode check REFCLK is applied correctly, e.g.,  for 26MHz input at REFCLK, REFCLK should be square-wave at VDDIO level, CFG pin tied to VDDIO.
• If input clock mode check CLOCK is applied correctly, 60MHz square wave at VDDIO level; and CFG pin tied to GND or VDDIO (don’t care which)

-       Verify DIR goes High->Low (~3ms after CS enabled, which indicates that TUSB1211 PLL has locked, and bus is now in TX mode, i.e., control is given to Link)
-       Verify 60MHz clock is observed on CLOCK pin
-       Verify VDD33, VDD15 LDO power supply outputs are in spec (3.1V, 1.5V respectively)
-       Verify IDDQ vs IDDQ table in TUSB1211 datasheet

• The objective here is to check that a reasonable current is being drawn from VBAT indicating that internal circuitry (PHY, PLL, biasing, etc) has powered up(if no current or a few 10’s of uA only were drawn this would indicate an issue).
• When TUSB1211 is powered on, the PHY circuitry will power up in FS synchronous mode albeit without data activity, and IDDQ should exhibit VBAT current draw slightly less than the 31mA given in the datasheet. Typically we measure  about 27mA in the lab.

-       Verify VBUS is at 5V

• This is just a check for VBUS presence in the system if this is possible before SW availability.
• In Device mode : VBUS is expected to be provided at the USB connector by the connected Host. Check (by probing if possible) VBUS arrives at TUSB1211 pin.
• In Host Mode: VBUS is provided by the Host system. If TUSB1211 PSW pin is used to control  an external VBUS source then VBUS will not be present unless SW has written to the DRVVBUS register bit. If TUSB1211 PSW pin is unused then check if elsewhere in  system VBUS is provided and is present.

-       Verify DIR goes High->Low
-       Verify VDD33, VDD18 LDO power supply outputs are in spec
-       Verify IDDQ vs IDDQ table in TUSB1211 spec

=> IMPORTANT:
Some informations regardin TUSB1211 are TI-Confidential, not for public distribution.
Could you please enter in contact with your TI Field Application Engineer in order to put an agrement in place? 

We went through and verified each of the steps.  Everything looked good, with the only exception being the DIR which doesn't seem to be low for much time other then a blip after power on and after we toggle reset.  Is there any additional guidance for making this chip work with a OMAP in host mode?  We'd really like to use this chip over the SMSC part used on the BeagleBoard.

Another question we had was if we could get the power sequencing information (Section 9.3.3.1) mentioned in the datasheet on page 14?

Again, i am refering to NDA doc regarding TUSB1211. This is TI-Confidential, not for public distribution.
Could you please enter in contact with your TI Field Application Engineer in order to put an agrement in place? 

I guess Salmi, Jake is your contact?

Yes Jake Salmi is my contact.  He provided me with a application guide and we evaluated that against our design.  I'll send him a copy of our schematic.