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TUSB2046BI 48 Mhz Jitter Spec
An ESR of around 100-200ohms would be good.
What do you mean with an ESR?
I was asking for a jitter spec ..?
Sorry, I thought you were going to use a crystal, didn't realize that there is an option to use 48MHz clock instead of a crystal for TUSB2046B. This is an old design, I'll have to digup specs to find out what the tolerance is on the internal PLL. Will get back to you soon on this.
I checked with our internal PLL design for TUSb2046B and the clock must meet the USB 2.0 full speed jitter spec as outlined in Table 7-9 of the full speed spec (available at http://www.usb.org/developers/docs/). The source jitter tolerance TDJ1 has to be between -3.5 (min) to 3.5 (max) ns. TDJ2 has to be between -4 to 4 ns.
Sounds good, thanks ..
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