The following question concerns the TUSB9261 usb 3.0 to sata bridge.
I have read the various datasheets and manuals of the device and in those documents it is said that the spi interface can operate over a frequency range 100KHz to 50 Mhz.
1. is the spi operating frequency (SCLK) is determined solely by the usb bridge or is it configureable, if so how?
2. i am especially interested in operating the spi interface at a frequency up to 200 Khz( preferably lower rate) , is it possible?
I apologize for the delay here.
The SPI clock frequency can be adjusted only by firmware.
Tell me your exact requirement and I will pass it to the software team to see if they can release a customized fw.
I understand that the spi clock frequency is adjustable via firmware. but i belive the initial communication clock frequency is hardware defaulted.
Can you tell what the initial clock frequency is set to? we require a 100 KHz maximum clock frequency (we can stretch our design up to 110 KHz, but it is not advised).
A customized fw would be most appreciated.
The SPI clock is fixed in the boot code at 18.75MHz.
Why is your design restricted to 110KHz?
BootROM is configured for 18.75MHz to read the FW image from SPI flash into RAM.
If you have some other SPI peripherial that is slower, you can change the SPI frequency in FW after it is loaded.
I use the same spi flash memory simultaneously for the 2 devices where the usb2sata is one of them. therefore i need the usb2sata spi clock to be considerably slower than the memory's.
the usb2sata boot process is required to be at a rate of 100KHz, is it possible?
I have another question regarding the the fw. does the device read the fw by reading consecutive addresses from memory, or it determines the next address to be read from data that was previously read ?
BootROM is "ROM" code (read-only) and cannot be changed so no, it is not possible to change the SPI frequency for bootup. SPI FW loading is done by reading consecutive addresses. Base address is sent and then reads are done until data load is complete.
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