I have problem with generating CLKOUT[6..0] on XIO2001.
I init XIO2001, write config registers and I want to make config cycles on PCI bus.
When I read config space on PCI bus signals CLKOUT begin generating on 5 cycles before generating signal FRAME#.
Some boards on PCI bus don't sense PCI bus cycles. If I repeat read config space on PCI bus this boards begin work?
Can you answer me, why signals CLKOUT begin generating on 5 cycles before generating signal FRAME#?
Could you send a register dump of the XIO2001 and your schematics. I'm afraid I don't understand quite well your problem, why do you say your PCI downstream device does not sense the clock?
Can you get a timing capture of the PCI signals?
Hello ELIAS, In my schematic I pullup signals CLKRUN_EN and CLKRUN# to 3,3V with 4,7kOhm - Clock run support enabled (how in datasheet)
When I desserted PERST# and GRST# signals CLKOUT[6..0] not generated. Clock Run Status Register = 0x01 (Secondary clock stopped).
But when I connected CLKRUN_EN to GND, signals CLKOUT[6..0] begin generated and all devices on PCI Bus work very good.
Can you tell me how I must connect signal CLKRUN_EN (to 3,3V or GND with resistor)?
With regards, ALex .
The clock run protocol will disable the PCI clocks to save power.
Do you need the clock run functionality?
If not, you must to disable the clock run protocol by connecting CLKRUN_EN to ground. Keep the pull-up on terminal CLKRUN#.
Also, don't forget to connect CLKOUT to CLK.
I connect CLKRUN_EN to ground, disable clock run protocol.
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