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Is there any reply for me? I don't have lots of time... Please ASAP...

I'm looking into this to be sure, but I expect it to only be a couple clock periods (<100ns when the clock is 50MHz).

Best regards,
RE

Thank you for your response.

But I don't think so because DES delay can be proportional to Tc. As you know, Tc=1/CLK. So if insreasing CLK, DES delay will be decreased. is it right?

According to your comment, CLK=50MHz is Tc=20ns, and then A couple of 20ns is 40ns of DES Delay. I cannot get 100ns when clock is 50MHz...

Please let me know the formular for DES Delay.

Thanks and Regards.

I said I expect it to be "<100ns" for less than 100ns.

I'd like to know why this data propagation delay is important to you.  Are you concerned about lag time for the user, or video/sound sync problems?  1 frame of lag at 60fps is 16ms; is it sufficient for you to know that the LVDS86A adds less than 0.0001ms?

Thanks,
RE

Many thanks for your reply.

DES delay is important to me because customer wants to use it like as the below diagram. SN65LVDS86A is added on only one path. So customer is considering to occur some delay between two monitors.

Now that you mentioned it, I agreed your comment. But my customer wants to know which specification SN65LVDS86A has for DES delay.

If you possible, please let me know it.

Thanks.

If you cannot explain the fomular for DES Delay, I'd like to know the maxium value of DES Delay at minimum clock. Is it 100ns?

Please help me to clear this issue.

Thanks.

Sorry for the delay.  We expect the data latency to be a low number of clock cycles.  It's an insignificant amount compared to the framerate (0.0001ms vs 16ms).

Thanks,
RE