ODCK clock for TFP401

Saravana kumar

Hi Team,

If I'm using screen resolution of 800 x 600 at screen refresh rate of 60Hz from the PC and I'm using DVI-D(Single Link) which connects to TFP401. What would be the ODCK frequency?

In other words, what is the factor determines the ODCK frequency?

Guru 76140 points

Elias Villegas M.
- Oct 24, 2016 5:07 PM
Hello,
The ODCK is approximately [(H_pixels)*(V_pixels)*(refresh rate)]+(blanking)
The blanking differs from graphics processor.
In your case it will be approximately 800*600*60=28.8 MHz plus blanking (usually from 10% to 15%)
Regards
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Prodigy 35 points

Saravana kumar
- Oct 25, 2016 1:52 AM
In reply to Elias Villegas M.:
Hi Elias,
Noted and thanks for your reply.
In my design, the ODCK clock always in approximately frequency of ~850khz regardless of any screen resolution. What could be the reason? Moreover, the VSYNC, HSYNC and DE signals always in the state of logic high, means to say, there is no any pulsing signal. Below are the pin configuration for the TFP401 that I've done thru a PLD:-

ST pin :- Logic High (+3.3v)
STAG pin :- Logic High (+3.3v)
DFO pin :- Logic High(+3.3v)
PIXS pin :- Logic High(+3.3v)
OCK_INV pin :- Logic High(+3.3v)
PD pin :- Unconnected
PDO pin :- Unconnected

Did I left off any of the configuration for the TFP401? Please advice.
Thank You.

Best Regards,
kumar
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Guru 76140 points

Elias Villegas M.
- Oct 25, 2016 7:17 PM
In reply to Saravana kumar:
Seems like the TFP401 is not detecting any valid signal on the TMDS inputs, what is the state of SCDT?
Can you provide scope captures of the TMDS signals?
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Prodigy 35 points

Saravana kumar
- Oct 26, 2016 4:04 AM
In reply to Elias Villegas M.:
Hi,
SCDT always Logic low at TFP401.
The TMDS signals from the PC's graphic card such as (Rx0+/-), (Rx1+/-), (Rx2+/-) and (RxC+/-) thru the DVI connector, all were in Logic High. Yet, when I connects the DVI cable from the PC to a LCD monitor, I'm able to get the display correctly(It's show that the graphic card works well). And I believed that the TMDS signals hardly capture by the scope.
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Guru 76140 points

Elias Villegas M.
- Oct 27, 2016 8:59 PM
In reply to Saravana kumar:
If SCDT is low that means that the TFP401 is not receiving a valid TMDS signal, the TMDS signals should NOT be static high, can you take a scope capture of the TMDS signals?
It looks like your TMDS source is not detecting the TFP401, can you provide your schematics?
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Prodigy 30 points

jianfeng he
- May 17, 2017 7:00 AM
In reply to Elias Villegas M.:

Hi, recently I have faced the same conditoin like you (connect PC with 401 thru a DVI connector ,but no valid signal be dected at 401 output pins,like ODCk),could you give me some advice on how to sovle it ?
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Guru 76140 points

Elias Villegas M.
- May 17, 2017 5:00 PM
In reply to jianfeng he:
Hello,
Please provide your schematic.
Does the HDMI signal contains embedded audio?
Have you tried multiple resolutions?
Regards
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Prodigy 30 points

jianfeng he
- May 18, 2017 2:49 AM
In reply to Elias Villegas M.:

Hello,thanks for your help!

My source is a DVI signal from a PC host and till now ,I have not tried any other resolution except the default(1920*1080/60HZ).

Best regards!
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Guru 76140 points

Elias Villegas M.
- May 18, 2017 5:02 PM
In reply to jianfeng he:
Hello,
The VESA standard pixel clock for a 1920x1080@60fps is 173MHz which is out of the spec of the TFP401.
Can you try with a lower resolution? Or you can adjust the FPS=50, that would give you a pixel frequency of 141.5MHz which is supported by the TFP401.
Regards
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Prodigy 30 points

jianfeng he
- May 19, 2017 2:28 AM
In reply to Elias Villegas M.:

OK，I will have a try!

But I did not find the VESA standards for 1080p.I just found a 1080p standard that is 2200(1920)*1125(1080)/60hz with the clock frequence 148.5MHZ.

Could you show me your VESA standards for 1080p?

Best regards
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ODCK clock for TFP401