• Resolved

TMDS181: 4K signak problem

Part Number: TMDS181

Hi TI,

I detected a 4K signal problem,

Under default condition of TMDS181EVM,

Pin

Items

set

1

HDP_SRC

JP 1-2 for not used

J3

I2_EN_PIN

JP 2-3 for pin strap

J4

SCL

JP 1-2 for USB IF TO I2C

J6

SDA

JP 1-2 for USB IF TO I2C

J7

A1

NC for weak internal pulldown

(Normal Mode)

J8

VSADJ

JP 1-2 for 6.8KΩ

J11

SIG_EN

JP 2-3 for Signal Detect Enable

J12

EQ_SEL_A0

NC for Adaptive EQ

J14

TX_TERM_CLT

NC for auto select of term

J15

PRE_SEL

NC for 0 dB

J17

SWAP_POL

NC for normal

Input 4K signal(Non HDCP)  to the EVM, Undre Hot plug condition of the input HDMI cable.  

Some time The output was NG(May be Lower rate signal is detected)  as lower picture.

 


   This is OK signal(4K)

This  is NG output signal( When  a Display receive the signal, it cannot draw a picture.)  

Do you estimate the origin of the problem ?

  

Thanks and Best Regards,
Kobayashi,Toshi
Fuji Electronics Co.,LTD.

 

  • Hi Toshi,

    I can't see the picture, could you attache it again?
    I don't really understand what is the problem, could you elaborate?
    For debugging, set SIG_EN=LOW
    In the PC, do you see the monitor listed all the time?
    What is the length of the cables?
    Do you have eye-diagrams to share or test reports?

    Regards
  • In reply to Moises Garcia:

    Moises, thank you for your reply.
    I'd like to send the pictures to you via message.

    Thanks and Best Regards,
    Kobayashi,Toshi
    Fuji Electronics Co.,LTD.

     

  • In reply to Toshi:

    Hi Toshi,

    The 5.7Gbps signals are at the input of TMDS181, right?
    The 1.54Gbps signals are at the output of TMDS181, right?

    Could you confirm the TMDS_CLOCK_RATIO_STATUS=1?
    Could you share scope captures of one TMDS_CLK period to see how many bits are in each CLK period?
    If you reset the device the problem is gone?

    Regards
  • In reply to Moises Garcia:

    Moises, thanks.
    >The 5.7Gbps signals are at the input of TMDS181, right?
    >The 1.54Gbps signals are at the output of TMDS181, right?
    yes, they are.

    I'll check the TMDS_CLOCK_RATIO_STATUS and send a scope capture later.

    Thanks and Best Regards,
    Kobayashi,Toshi
    Fuji Electronics Co.,LTD.

     

  • In reply to Toshi:

    Hi Toshi,

    If the data rate belongs to HDMI2.0, TMDS_CLOCK_RATIO_STATUS has to be set to 1 to avoid frequency division in data lanes.

    Regards
  • In reply to Moises Garcia:

    Moises, thank you for your help via mail,
    We try to avoid the problem by using the HPDSNK_GATE and it was fine up to today.

    Thanks and Best Regards,
    Kobayashi,Toshi
    Fuji Electronics Co.,LTD.