SN65DP159: Unable to lock PLL

Part Number: SN65DP159


I am using our custom dev. board for DP159 in x-mode, that is exactly the same, as your EVM, only connectors are diferrent.

Using SLLA358 as a guide, i have troubles with locking PLL (4.3.1).

Only value, I am reading from address 0x00 on page 1 is 0x03.

Can you give me an advice about this?


V. Svoboda

5 Replies

  • Hi,

    Our DP159EVM wasn't designed for x-mode operation, did you make the required hardware changes?
    Can you see the display listed in the PC?
    Could you confirm the link training clock recovery phase is implemented properly?

  • In reply to Moises Garcia:

    I am sorry for confusion, our board can be configured to be used as DP retimer.
    Example implementation from SLLA358 was taken into account.
    Display is listed in PC and training clock recovery phase is copied from SLLA358.

    SN65DP159_CONF(0x10, 0xF0), // Disable TX lanes
    SN65DP159_CONF(0x00, 0x02), // Enable Bandgap, DISABLE PLL, clear A_LOCK_OVR
    SN65DP159_CONF(0x01, 0x01), // CP_EN = PLL (reference) mode
    SN65DP159_CONF(0x0B, 0x33), // Set PLL control
    SN65DP159_CONF(0x02, 0x3F), // Set CP_CURRENT
    SN65DP159_CONF(0x30, 0x0F), // Set RX Lane count 4
    SN65DP159_CONF(0x00, 0x03), // Enable Bandgap, Enable PLL, clear A_LOCK_OVR
    SN65DP159_CONF(0x4C, 0x01), // Enable fixed EQ
    SN65DP159_CONF(0x4D, 0x08), // Set EQFTC and EQLEV (fixed EQ) - HBR2

    V. S.
  • In reply to user4962877:

    After this sequence, are you sending TPS1 pattern?
    TPS1 is just a clock at half the data rate; for 5.4Gbps, the pattern is a 2.7GHz clock.

  • In reply to Moises Garcia:


    I am not even sure if TPS1 is sent automatically by source, or sink have to send request.
    Is there an option like DP130s access to DPCD through I2C?
    I have no equipment, I can use to monitor what is really happening on DP lines.

    Sorry for my ignorance..
    DP130 configuration now looks like a piece of cake.

    V. S.
  • In reply to user4962877:


    DP159 has no DPCD monitoring, AUX channel is connected directly from DP connector to DP receiver.
    TPS1 is sent by the source after AUX channel has been stablished.

    This is going to be hard to debug without measurement equipment
    Have you tried different EQ levels?
    Have you tried different resolutions(data rates) and different configuration on DP159(HBR2, HBR, RBR)?
    Do you have a signal generator to test a stand alone clock?