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Question about TFP401

Guru 19495 points
Other Parts Discussed in Thread: TFP401

Please let me know two points about TFP401.

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・I don't understand difference between 1-pixel/clock mode and 2-pixel/clock-mode well.

1-pixel/clock mode outputs it as ODCK input (pixel clock) and I think that the data are output only by the QE side (the QO side is not output), is it right?

・Is there the method to know whether the format of input data (picture data, etc) is input normally?

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Best regards,

Satoshi

  • The output format of the TFP401 is not related to the input, so any input can be output in 1pixel/clock or 2pixel/clock.

    If configured as 1-pixel/clock, both pixels even and odd will be output on QE[] bus every clock cycle(ODCK), one at a time, this is, the pixel-0 will be output on the first clock cycle and pixel-1 on the second clock cycle and so on.

    If configured as 2-pixel/clock then the even pixels will be output at the same time on the QE[] bus and the odd ones on the QO[] bus every clock cycle.

    Regards.

  • Hello Satoshi,

    Take a look at this App note DVI/HDMI to LVDS.  I found it useful and it will give you a picture of what Elias has explained.

    http://www.hobbielektronika.hu/forum/getfile.php?id=164305

    Thanks,

  • Thank you for reply,

    And I'm sorry, I studied, but I was not made an image of DVI , because DVI was difficult.

    Are there any other application note?

    I'm appreciate if there are application data shown especially by a diagram.

    Best regards,

    Satoshi

  • Hello Satoshi,

    What exactly are you trying to do? 

    1. What type of LCD are you trying to interface with?
    2. Have you looked at the differences between DVI and HDMI?
    3. How are you generating the RGB and control signals?

    Thanks,

  • Dear Greenja-san

    Sorry to be late.

    I replie to below.  

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    ・What type of LCD are you trying to interface with?

    ⇒It is not going to connect with LCD but is going to connect with FPGA.

    Customer think that it will convert the interface for FPGA input to customer's LSI input.

     

    ・Have you looked at the differences between DVI and HDMI?

    ⇒RGB and control signal of TFP401 are inputted by DVI.

    (Business-oriented)PC is generating the DVI signal.

    (The graphics card of the PC is generating RGB and the control signal of TFP401.) 

     

    ・How are you generating the RGB and control signals?

    ⇒The DVI signal is a DVI-Dual signal, and customer separated DVI-Dual by a certain method,

    and think that it will process by two TFP401.

    In that case, DVI-Dual enters in a format as special as 1920x2160 / 60 Hz.

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    Best regaeds,

    Satoshi