TL16C550 generate a interrupt without data ready flag in LSR register.

Thomas Chang15933

Expert 4770 points

Other Parts Discussed in Thread: TL16C550D, TL16C550C

Dear Team:

As we know in general, UART FIFO timeout of 16C550 will generate a interrupt with data ready flag of LSR register.

Then the UART driver can receive corresponding data until the data ready flag disappear.

We meet a weird situation. 16C550 generate a interrupt without data ready flag in LSR register.

Without data ready flag, UART driver won't receive data from RX buffer.

Further, we didn't know the how many data in receive FIFO.

Thus, interrupt will trigger again. So our system will be hanged due to the interrupt lock of FIFO timeout.

This might happen in couple days or couple hours.

This is a urgent issue from our customer.

Could you please give me your comments ?

over 9 years ago

0 John Griffith over 9 years ago

TI__Mastermind 21336 points

Hi Thomas,

I am going to move your question to the Consumer and Computing forum so that it can get the proper support and visibility. They should be able to address you question.

Thanks!

John

0 Diego Cortes over 9 years ago

TI__Mastermind 36085 points

Hello Thomas,

In order to help you with the issue I would to know two things:

The exact value on the Interrupt identification register when the issue occurs.
The configuration process used to setup the UART.

Also please confirm which part number are you using (TL16C550D or TL16C550C).

Best regards,

Diego.

0 Thomas Chang15933 over 9 years ago in reply to Diego Cortes

TI__Expert 4770 points

Dear Diego:

The part number is TL16C550DPTRG4.

I will check your 2 points with customer.

0 Thomas Chang15933 over 9 years ago in reply to Thomas Chang15933

TI__Expert 4770 points

Dear Team:

I got customer reply as below and need your supporting quickly.

1.The exact value on the Interrupt identification register when the issue occurs.

All the values of related register:

IRQ Line status LSR: 60

IRQ IER: 5

IRQ IIR: cc

IRQ MSR: f0

IRQ SCR: 49

IRQ LCR: 1b

Attached file is the detail log for the interrupt lock. Please refer to it.

2.The configuration process used to setup the UART.

Following is the platform information:

CPU: MIPS IDT-438

OS: Linux 2.4.18

Driver: Original Linux serial driver in IDT-438

For the configuration process, I think it's a standard process to setup the UART.

In other words, it follows Linux standard to initialize UART like doing identification..set clock & baud rate .. interrupt sharing... etc

For the weird circumstance of FIFO interrupt without data ready and from the view of ASIC design....

What kinds of condition or abnormal operation will cause this problem...

Please help to advise...

0 Joel Jimenez0 over 9 years ago in reply to Thomas Chang15933

TI__Mastermind 18655 points

Hello Thomas,

We need a further description of the configuration process used to setup UART registers.

Regards.

0 Thomas Chang15933 over 9 years ago in reply to Joel Jimenez0

TI__Expert 4770 points

Hello Joel:

I post the web link about customer configuration as below.

https://drive.google.com/file/d/0BwciLmxybehvSHFJbnpjZ1R1cXc/edit?usp=sharing

0 Thomas Chang15933 over 9 years ago in reply to Thomas Chang15933

TI__Expert 4770 points

Hi Joel:

I pasted thecircuit for your reference.

0 Thomas Chang15933 over 9 years ago in reply to Thomas Chang15933

TI__Expert 4770 points

Dear Team:

FCR register is 0x81, and the trigger level of FCR is 8 bytes.

Yesterday we visited customer to narrow down question as below.

Question is: what kind of condition IIR=CC (character time out indication), Data ready of LSR is zero flag?

If TL16C550D had the behavior, what is our suggestion?

Is MCU directly to read data and ignore data ready flag? Or other way?

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TL16C550 generate a interrupt without data ready flag in LSR register.