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TUSB1310 ulpi clock problem

Other Parts Discussed in Thread: TUSB1310

Hello everyone,

I met a problem when I try to use TUSB1310 on my Xillinx FPGA.

According to the datasheet, the output ULPI_CLK should be 60MHz.

I input a 40MHz xstal clock on pin "XI", and I set the ULPI_DATA[5:4] to 2'b11 when PHY_RESETN and RESETN are

de-assertion.

But it looks like no matter which value I set to ULPI_DATA[5:4] when I reset TUSB1310, the output ULPI_CLK always

is 120 MHz.(I have try 2'b00 and 2'b11)

Seems like it didn't catch my strap setting.

Any suggestion for me?

Thank you

Chiayu Lu