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Excessive power consumption with TFP401A-EP

Fred P
Expert 2015 points
Other Parts Discussed in Thread: TFP401A-EP, DS16EV5110

I have a TFP401A-EP whose inputs are driven by an equalizer DS16EV5110.
No DVI source is connected to the equalizer.  Both lines of its output clock pair are idle at 3V (goes up to 3.3V is the EQ is powered down).
So far that looks ok for me.

Meanwhile, the TFP401A-EP outputs chaotic signals (3.3Vpp noise) on all data lines while the output clock (ODCK) line outputs some kind of 300MHz sine wave full of jitter and with some glitches on the peaks.

DE output tries to go down from time to time but so briefly that it does not even reach GND.

My scope has 1GHz BW and I am properly probing with a GND spring.  It is unlikely to be a measuring issue.

It also heats a lot.  My estimation is around 600mW power consumption for the TFP401A-EP and the EQ together.

That does not look good to me.

Is that an expected behavior?

 

Regards,

Fred

  • 0
    TI__Intellectual 1805 points

    Hello Fred,

    No, that's not an expected behavior. Could you attach your schematic please? I think it's an electrical issue. 

    What are the resistor values at the TMDS terminations?

    Which is the IC that are getting hot? Could you measure its temperature?

    Is your circuit working properly when you connect a DVI signal?

    Regards,

    Aldo

  • 0 in reply to Aldo Acero
    Expert 2015 points

    Hi Aldo,

    I'll provide the schematic but to you only.

    How can I do that?

    Fred

  • 0 in reply to Fred P
    TI__Intellectual 1805 points

    Hi Fred,

    Send it to my email address.

    aldo.acero@ti.com

    Regards, 

    Aldo

  • 0 in reply to Fred P
    TI__Guru 71516 points

    Hello Fred,

    In finding a solution to the overheating condition you are seeing, we need more information to assess a possible solution.   

    1. Please provide 'scope captures of the DVI outputs of U34 (RX inputs to U32), data and CLK.  If you have a differential probe, please provide the differential signals.  Two sets would be desirable, one set with normal operation, one with 'no signal' condition.  And if you can relate, or confirm, the overheating occurs with the 'no signal' condition, to a specific set of 'scope captures.

    2. Next, modify the circuit as follows:  Connect U32 SCDT pin 8 to PDO pin 9.  Verify under the same conditions above that created the overheating, this now does NOT occur. 

    3. Finally, back to step 1, if there are random signals or "noise" seen on the outputs of U34 when there is an absence of input signal, add a pull-down termination to CLK- (pin 1) and verify the "noise" is no longer present.  With the noise removed now from the circuit, verify U32 no longer overheats.

    We have not seen this behavior with the TFP4xx family, so we are at a loss as to why this might be occurring with your circuit. 

    ~Leonard 

      

  • 0 in reply to LeonardEllis
    Expert 2015 points

    Hi Leonard

    All the points you mention have been covered offline with Aldo Acero (above).

    Please contact him and join in the ongoing investigation.

    Regards,

    Fred

  • 0 in reply to Fred P
    TI__Intellectual 1805 points

    Hi Fred,

    Leonard already have the scope captures and all the information you sent me days ago. He require the new ones he specify, please provide him with those. And put special attention to the point 3, it could lead us to a possible solution.

    Regards,

    Aldo.

  • 0 in reply to Aldo Acero
    Prodigy 110 points

    Hi Aldo,

    I'll do my best to provide you screen shots today or at the latest by tomorrow end of day.

    Best Regards,

    Sylvain

  • 0 in reply to LeonardEllis
    Prodigy 110 points

    Hello Leonard,

    What value of pull-down do you suggest for point 3 ? 10k, 100k ?

    Thanks,

    Sylvain

  • 0 in reply to Sylvain Poulin
    TI__Guru 71516 points

    Hi Sylvain,

      The idea is to ensure the CLK circuit does not respond to noise when the input is open; since there is a 50-ohm internal termination to VDD on each pin in the DS16EV5110, start with a 1k-ohm CLK- IN to GND, and monitor the CLK output.

      The 1k-ohm will give you about 160mV differential CLK+ to CLK-, and you may have to make that somewhat higher; 500-ohm will give you 300mV.

    ~Leonard  

  • 0 in reply to LeonardEllis
    Prodigy 110 points

    Hi Leonard,

    I forwarded the screenshots to Aldo as I don't have your email address. This is for the point 1 of your previous posting.

    For point 2, the SCDT connected to PDO pin doesn't change anything ... the SCDT is always High because it detects valid signals at the inputs... the overheating is still there as expected.

    For point 3, I added the 1k Ohms PD and the overheating disappeared. However, this fix is changing the eye opening of the signal and it will probably create problem during Qualification Susceptibility testing (Conducted, Radiated, lightning, etc). The common mode rejection is most probably impacted ...

    Sylvain

  • 0 in reply to Sylvain Poulin
    TI__Guru* 88835 points

    Greetings,

    How about if we put 10 Ohm Resistor in series with the TMDS clock pair on the input of the DS16EV5110? I suppose perhaps we can put this on the driver side. DS16EV5110 has very low input sensitivity and perhaps we can attenuate this noise. We can start with 10 Ohm and perhaps even increase this value. I don't know the nature of this noise, another potential solution would be to put a small Cap(start with 0.1pf) across P & N to see if this can short out this noise.

    Regards,,nasser