SN65LVDS324 output timing

Hi Diego,

Thank you for your fast reply.

I will feedback to my customer the information.

Thanks,

Naoki Aoyama

Our customer requirement is 12MP resolution camera interface to DM8168 with SN65LVDS324.

Request you to clarify below queries on SN65LVDS324:

1. Does this chip downscale the high resolution video to 1080p60.In our case it is 4K x 3K resolution?If we see in the datasheet of LVDS324 it does not have any IPU block to downscale image process.It has just clock multiplier to support subLVDS to parallel?

2.Sony CMOS sensor(IMX144CQJ) has 10ch subLVDS of each 10/12-bit and supports drive mode as below:
  1. 4000 x 3000@ 35fps,12-bit
  2. 4000 x 3000@ 40fps,10-bit
Whether these two modes can be supported by LVDS324?

3.LVDS324 datasheet says subLVDS inputs Support Up To 648Mbps.Whether 648Mbps is per channel,then it has 12ch subLVDS of total 7776Mbps rate?

4. what is the max sony resolution sensor is interfaced to LVDS324?

5. What does 8K x 8K frame size support means in LVDS324?

Looking forward for your answer

Regards

B. Eshak

Hello Diego

Thanks for the reply.

1. So interfacing the DM8168 to 12MP camera via LVDS324 is feasible?

2. If it does not have down scaling feature.Then how does it can take up high resolution video frames and convert it to 1080p60.Please brief on this.

3. You said "The Actual throughput for the SONY LVDS parallel mode is 1944 Mbps for 12 bpp and 1620 Mbps dor 10 bpp." How does this numbers calculated.?
4. Is 1944Mbps and 1620Mbps is total throughput for 10ch interface?

5. Iam not sure on the operating frequency of Sony image sensor for both the modes. Its says the input frequency to sensor as 72Mhz. Is it input or output clock ?

Please refer the below link for datasheet.

6. How to calculate theoritically whether the two modes of sony image sensor can be interfaced to LVDS324?

7. Please explain with an example of taking more resolution camera like 5MP or more , what  LVDS324 does on camera input side and output to processor at 1080p60.

8. Is that the camera should be set to 1080p resolution so that LVDS324 can output 1080p60 to processor.?

Regards

B. Eshak

Hi,

I am using DM8168 processor. I am trying to bring up Sony Camera (IMX136LQJ) in my customized platform.
I am using SPI interface to configure the Sensor. Currently I can able to do proper configuration and I am getting the expected Pixel clock from Sensor. I am using LVDS chip (SN65LVDS324) to send the data from sensor to processor.

Once the camera is initialized, I couldn't get any HS/VS signals and data from LVDS chip. But I am getting these signal only if I configure the TEST_MODE bit in the SENSOR_CFG register (0x9).

And also I couldn't capture any data from my application (saLoopBack).

Please answer for my below queries also:

1. Which output format will the LVDS will pump to the DM8168 processor?

2. Whether DM8168 supports this LVDS ouput format?. If so, where I have to configure the same in S/W code?.

3. What for this TEST MODE is made and it is possible to capture from processor to get this data?

Please suggest me some solution to resolve this issue.

Thanks in advance.

Regards,
Salih

Hi Diego,

Thank you very much for your prompt reply. The image sensor IMX136 output format is Low-Voltage LVDS parallel with 60Fps 1080p of resolution. Could please suggest me on how to make it work with processor?..

Thanks in advance.

Regards,
Salih

Hi,

Thank you very much for your response.

bits 5 & 4: according to the DM8168, please check the sync polarity and the color mapping on the processor.

For the above bits, you mean about VIP port configuration in processor?. There are nine sync modes and sync polarity is also there.

Which one I have to set it in the processor side?. If I configure the sync polarity as high in LVDS chip, then should I set the same in VIP port configuration ?. What is color mapping?.. Are you mean about the input data format for the processor?

Thanks in advance.

Regards,
Salih

Hi Diego,

Thanks for your inputs. But, during the TEST mode the LVDS giving BAYER RAW format as output. In my processor, this format is not supported. Actually my issue is, when I disable the TEST mode in the LVDS chip, I am not getting HS/VS signals. I don't know what might be the reason for this issue.

I am struggling with this issue for very long time. Please suggest me on how to make it overcome this issue.

Thanks in advance.

Regards,
Salih

Hi Diego,

I am getting the input clock frequency properly without any fluctuations. Here, I am not getting the HSYNC and VSYNC signals.
I am still not sure where is the issue, whether it is with the LVDS chip or with my sensor.

Please suggest me any solution to solve this issue.

Thanks in advance.

Regards,
Salih

Dear Diego,

Thanks for your inputs. Do you asking about the pixel clock (output clock) of the sensor?.
I am getting the stable pixel clock without any fluctuation.

Regards,
Salih

Dear Diego,

Yes, I am getting the stable output clock (148MHz) from the LVDS chip without any fluctuations. But the HS/VS signal is not pulsing.

Thanks in advance.

Regards,
Salih

Hello,

Can you please let us know the CLKOUT frequency when LVDS324 is configured in the test mode? We are programming it with the following:

0x28 - > 0x03

0x09 -> 0x64 (test mode)

0x0A -> 0x22

Thanks,

Akhil