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SN65LVDS324 HSYNC and VSYNC timing

Hello,

My customer uses the SN65LVDS324 and has a question.

He sets a blanking period at the beginning of video frame.

Does it assert VSYNC and HSYNC at the same CLKOUT?

Regards,

Naoki Aoyama

  • Sorry,

    I don't understand the question, can you elaborate more on the issue customer is having, do you mean the same CLK edge?

    The LVDS324 will assert/deassert VSYNC and HSYNC based on the start-of-frame and star-of-line/end-of-line respectively at leas one CLK cycle, the SOF and SOL/EOL are controlled by the Sensor not by the LVDS324.

    Regards.

  • Hello Elias,

    Thank you for your reply.

    I will check the sensor output format.

    Thanks.

    Naoki Aoyama

  • Dear Elias,

    We are using a new sensor which can provide the SOF/SOL/EOF/EOL to LVDS324. But we cannot find details from LVDS324 spec.

    I notice you comment that "The LVDS324 will assert/deassert VSYNC and HSYNC based on the start-of-frame and star-of-line/end-of-line respectively at leas one CLK cycle, the SOF and SOL/EOL are controlled by the Sensor not by the LVDS324."

    May I know what's these code defined in the LVDS324 for the pairing, please?

    Currently, we tried various value for SOF/SOL/EOF/EOL, We can got the right duration from LVDS324 but we cannot got the right timing from Vsync and Hsync.

    LVDS324 output details as below:

    CLK: 135Mhz/~7.5ns

    Hsync: 15us

    Vsync: 33ms

    There are around 2000 CLKs in one period of Hsync. But There are around 70 Hsync pulse in one period of Vsync.(There should be 1100 as we feel)

    Thanks very much for your help.