Hello, I have a big problem. Please Help me.
I would like to configure the SN65DSI86 chip to drive LCD.
LCD interface specification is 3.24Gbps 4lane.
resolution is 2732x2048, 24bpp, and dot clock is 400Mhz.
Then, there must be 12.96Gbps output by SN65DSI86.
However, the maximum input of SN65DSI86 is 12Gbps(1.5Gbps x 8lane).
I was thinking that used single SN65DSI86 is impossible to drive the LCD.
So the use of the two SN65DSI86.
SN65DSI86 each is responsible for 2 lane.
The LCD Main-Link0,1 connected ML1P / N and ML0P / N of first SN65DSI86,
LCD Main-link2,3 connected ML1P / N and ML0P / N of second SN65DSI86.
AUX Channel is connected to the second SN65DSI86.
Is it possible to "link training" in such a case?
This is a mistake of the hardware configuration?
AUX Channel works very well. Read edid, Read DPCD etc.
Main-Link always is not work.
If Input timing of DSI(MIPI) is the same.
Is there any method to use the without link training?
