P/N TL16C750, UART, setting the 64 byte FIFO enable (FCR register bit 5)

I have reviewed the datasheet regarding wetting this part into 64 byte FIFO mode.  We are polling the part, and the baud is 115.2k, 1 start, no parity 2 stop, and 8 data.

Our code currently has LCR MSB=0 before these two writes to FCR:

FCR = 0xF1

1msec delay

FCR = 0xF7

When reading back FCR we read 0xC1, so bit 5 is not set when LCR MSB = 0

on page 23 of datasheet: Access to FCR bit 5 require LCR bit 7 = 1, on page 24, in Bit 5: A write to FCR bit 5 is protected by setting the line control register(LCR) bit7  = 1.  This is ambiguous.  

I have also tried:

LCR = 0x80

FCR = 0x1

FCR = 0x21

then used the existing code

LCR = 7

FCR = 0xF1

1msec delay

FCR = 0xF7

But again bit 5 is not set.  Is the FCR register able to read all the bits, because what was read back was 0x12.

Please advise to the correct procedure to writing to this register, reading it, and especially setting bit 5.

Thanks,