XIO2001 Power-up/ Down Sequencing (Datasheet SCPS212H- MAY 2009- REVISED AUG 2014)

Chun Ling Chen

Other Parts Discussed in Thread: XIO2001

Refer to the datasheet PDF page 21, figure 4: Power-up sequence.

Question:

What is the timing requirement for the signal GRST# during the power-up?

From the section 6.12.1, it seem like the spec, wait 100us delay for Ref Clk stable & wait 100ms delay after power supply stable before PERST# deassertion.

Is it necessary for the GRST# to deassert at the instant after the power ramp up?

Can both GRST# & PERST# deassert at the same time?

Thank you.

over 9 years ago

0 Elias Villegas M. over 9 years ago

TI__Guru* 76130 points

Hello,

The GRST# terminal must be de-asserted after both 3.3V and 1.5V supplies are stable and valid.
We recommend to connect GRST# to a 1.5V Power-good signal.

Regards

0 Chun Ling Chen over 9 years ago in reply to Elias Villegas M.

Prodigy 200 points

Thanks but i am still expecting the response on the other question above.

Is there any reason why GRST# & PERST# could not be "deasserted" at the same instant?
I dont see any problem as the long as the XIO2001 is still under the "reset" state. Unless there's a specific requirement between the GRST# & PERST#.

Do let me know so that i could make a better decision on the circuit design.

Appreciate your reply.

0 Elias Villegas M. over 9 years ago in reply to Chun Ling Chen

TI__Guru* 76130 points

Yes,

GRST# and PERST# could be de-asserted at the same time as long as the timing requirements are met for both signals.
Regards

0 Chun Ling Chen over 9 years ago in reply to Elias Villegas M.

Prodigy 200 points

0 Chun Ling Chen over 9 years ago in reply to Chun Ling Chen

Prodigy 200 points

IF both GRST# & PERST# deasserted at the same time, the timing requirements would look like the above picture. Is this the timing requirements that you are referring to? OR there is other timing requirement that is not shown in the above picture?
Thank you!

0 Elias Villegas M. over 9 years ago in reply to Chun Ling Chen

TI__Guru* 76130 points

Correct, this is what I am referring to, in that war PERST# will meet the timing requirements.
Regards

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XIO2001 Power-up/ Down Sequencing (Datasheet SCPS212H- MAY 2009- REVISED AUG 2014)