Our customer has a question about XIO2001.
I'm posting the question for the customer:
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Our customer have designed PCI Express board now.
When they checked Read Access Speed of their designed board using XIO2001 with single access of 2bytes,
the board was slower in access speed than the other board via PCI Express-PCI bridge.
It is a problem that the board is slower than "via bridge".
So they have two questions about XIO2001.
#1
PCIe specifications have "AckNak Latency Timer" rules.
They think the AckNak Latency Timer rules affect a large latency of their board.
When the bridge designed by the same rules, it should also become equal to the board in delay.(but not same)
Specification of the bridge seems to be defined in the "PCI Express to PCI/PCI-X Bridge Specification".
QUESTION;
Please tell us what is the design of XIO2001.
(Was XIO2001 designed with "AckNak Latency timer rules" or "PCI Express to PCI/PCI-X Bridge Specification"?)
#2
Because to read Completion Data after ACK is returned after time of "AckNak Latency Timer"
according to their own specification of PCI Express board, it takes time of the 650nS for that more
before completion data is returned after Ack is returned.
So if it read Completion Data during the period of "AckNak Latency Timer" after accepting a READ request,
it can reduce time of the 650nS.
QUESTION;
Please tell us what is the design of XIO2001.
(Is XIO2001 a design like the above?)
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Thanks in advance.
Best regards,
Takishin
