SN65LV1224B wrong output with lock condition?

Paul Schoenke

Other Parts Discussed in Thread: SN65LV1224B

Hello:

We are having issues with the TI SN65LV1224B. We are getting a false lock. We believe it is a receiver IC “functional issue” and not an electrical issue. We think it has to do with RMT (see page 3 of the datasheet). Simply put, if we put in all zeros on the TX pins…we get non-zero’s out of the RX pins and the device is showing lock. This means we have data that is bad but the IC says is good.

The part looks to require a very tight clock. I found this post on the TI E2E:

https://e2e.ti.com/support/interface/high_speed_interface/f/138/t/355924

The timing device is @ 50 ppm:

http://www.digikey.com/product-detail/en/SG-210STF%2012.5000ML/SER3816-ND/4692602

I have a pretty good understanding of the whole RTM issue, however,

a) I do not understand why it would fail with all 0’s or all 1’s as received data since this does not fit the RTM profile

b) Does TI have an algorithm to help encode/decode data to prevent an RTM issue from occur? We do have a CPLD on each side so we can try to implement this functionality

We have reviewed the datasheet many times. The datasheet does not describe the RTM issue significantly enough or stress its importance. Does this apply only to synchronization?

I can send a BOM and schematic in also if that would help.

We can also get a few scope shots of the receiver data into the LVDS pins.

Any feedback or input is welcomed and appreciated!

Thanks again!

Paul

over 8 years ago

0 Paul Schoenke over 8 years ago

Expert 1375 points

Since my initial dialogue above, we figured out a few things on our side on the “bad valid data”. However, we are still have an issue with RMT. If we send standard 8b/10b data through the device, will this keep the system “correctly locked” or do we need to look further?

0 Elias Villegas M. over 8 years ago in reply to Paul Schoenke

TI__Guru* 76130 points

Moving to high-speed interface

0 Gerardo over 8 years ago in reply to Elias Villegas M.

TI__Genius 11280 points

Hello Paul,

Please send your schematic.

Regards,

Gerardo

0 Paul Schoenke over 8 years ago in reply to Gerardo

Expert 1375 points

Hello Gerardo,

We just figured some stuff out on our end. The fiber device we have has an automatic gain circuit in it which will cause it to give a wrong answer if the average of 1’s and 0’s is near 50%. This isn’t specified in their datasheet.

However, I believe that we still have an issue with RMT. For this device, how long until the device will “unlock” for “false lock” if an RMT pattern exists after a normal “sync pattern” lock?

Thanks again!

Paul

0 Paul Schoenke over 8 years ago in reply to Paul Schoenke

Expert 1375 points

Hello Gerardo,

For this device, how long until the device will “unlock” for “false lock” if an RMT pattern exists after a normal “sync pattern” lock?

Thanks again!

Paul

0 Gerardo over 8 years ago in reply to Paul Schoenke

TI__Genius 11280 points

Hello Paul,

I don’t have any answer yet from the design team, but I will send a reminder. I will get back to you as soon as possible.

Regards,

Gerardo

0 WIN Maung over 8 years ago in reply to Paul Schoenke

TI__Expert 3625 points

Paul,

Sorry for the delay, From what we can tell from the description of the RMT detection, once the deserializer is normally locked the RMT will not change the state and /LOCK pin will stay low. /LOCK does not go high until 4 consecutive stop/start cycles is missed.

RMT detection will help in the initiail lock phase and impact the lock time.

Let me know if this helps.

It will be helpful to get a latest summary of the issues after your findings with the optical device and what not.

regards, win

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SN65LV1224B wrong output with lock condition?