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DSI86 how to setting the clock source from REFCLK_FREQ

Other Parts Discussed in Thread: TEST2

Dear Sir,

We use REFCLK_FREQ 26MHz, write 0x0A = 04, but read the 0x0A = 05,   0x12 = 53 0x13=53

How to setting DPPLL_CLK_SRC = 0?

  • Hello, 

    When the 0x0A.0 bit is enabled the device is detecting a correct clock on REFCLK pin. Could you please send a scope capture of the input reference clock?

    Regards

  • Dear Sir,

    Setting the 0x0A = 04, it is clock from REFCLK pin and 26MHz, right?

    We will scope capture of the input reference clock late.

  • Yes, by programming 0x4 to 0x0A register will enable the REFCLk as the source clock, at 26Mhz.
  • Dear Sir,

    How to setting the color bar output?

    0x5A bit3 VSTREAM_ENABLE = 0
    0x96 [3:0] = 0001
    0x3C = 10

    Right?

  • Hello, 

    That's correct. In addition to the fields you mentioned, the active video size of the color bar has to be determined by the values programmed into the Video Registers (Table 22).

    The attached file is an example  I2C script that configures the DSI86 registers to enable the color bar mode. 

    2DP_4DSI_RBR_800x600_colorbar_enabled.xml
    <aardvark>
        <configure i2c="1" spi="1" gpio="0" tpower="1" pullups="0"/>
        <i2c_bitrate khz="100"/>
    
    ======Page 7======
       <i2c_write addr="0x2D" count="1" radix="16">FF 07</i2c_write> />
    
    ======ASSR Control to RW from R-only.  TEST2 pin must be high at rising edge of EN pin ======
       <i2c_write addr="0x2D" count="1" radix="16">16 01</i2c_write> />
    
    ======Page 0======
      <i2c_write addr="0x2D" count="1" radix="16">FF 00</i2c_write> />
    
    ======Disable HPD======
      <i2c_write addr="0x2D" count="1" radix="16">5C 01</i2c_write> />
    
    
    ======Single 4 DSI lanes======
    
      <i2c_write addr="0x2D" count="1" radix="16">10 26 </i2c_write> <sleep ms="10"/>
    
    ======DSI CLK FREQ======
    
      <i2c_write addr="0x2D" count="0" radix="16">12 </i2c_write> <sleep ms="10"/>
       <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>
    
    
    
    ======enhanced framing======
    
      <i2c_write addr="0x2D" count="1" radix="16">5A 04 </i2c_write> <sleep ms="10"/>
    
    
    ======ADDR 0x93 CFR======
    
       <i2c_write addr="0x2D" count="0" radix="16">93</i2c_write> <sleep ms="10"/>
    
    ======Read======
        <i2c_read addr="0x2D" count="6" radix="16">00</i2c_read> <sleep ms="10"/>
    
    ======Pre0dB 2 lanes no SSC======
       <i2c_write addr="0x2D" count="1" radix="16">93 20</i2c_write> <sleep ms="10"/>
    
    ======L0mV RBR======
       <i2c_write addr="0x2D" count="1" radix="16">94 20</i2c_write> <sleep ms="10"/>
    
    ======POST2 0dB ======
       <i2c_write addr="0x2D" count="1" radix="16">95 00</i2c_write> <sleep ms="10"/>
    
    ======PLL ENABLE======
       <i2c_write addr="0x2D" count="1" radix="16">0D 01</i2c_write> <sleep ms="10"/>
       <i2c_write addr="0x2D" count="0" radix="16">0A</i2c_write> <sleep ms="10"/>
       <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>
    
    
    
    ======Semi-Auto TRAIN ======
       <i2c_write addr="0x2D" count="1" radix="16">96 0A</i2c_write> <sleep ms="20"/>
    
    
    ======ADDR 0x0A CFR======
    
       <i2c_write addr="0x2D" count="0" radix="16">96</i2c_write> <sleep ms="20"/>
    
    ======Read======
        <i2c_read addr="0x2D" count="1" radix="16">00</i2c_read> <sleep ms="10"/>
    
    =====CHA_ACTIVE_LINE_LENGTH=======
        <i2c_write addr="0x2D" count="2" radix="16">20 20 03</i2c_write> <sleep ms="10"/>
    
    =====CHA_VERTICAL_DISPLAY_SIZE=======
        <i2c_write addr="0x2D" count="2" radix="16">24 58 02</i2c_write> <sleep ms="10"/>
    
    =====CHA_SYNC_DELAY=======
        <i2c_write addr="0x2D" count="2" radix="16">28 00 00</i2c_write> <sleep ms="10"/>
    
    =====CHA_HSYNC_PULSE_WIDTH=======
        <i2c_write addr="0x2D" count="2" radix="16">2C 80 00</i2c_write> <sleep ms="10"/>
    
    =====CHA_VSYNC_PULSE_WIDTH=======
        <i2c_write addr="0x2D" count="2" radix="16">30 04 00</i2c_write> <sleep ms="10"/>
    
    =====CHA_HORIZONTAL_BACK_PORCH=======
        <i2c_write addr="0x2D" count="1" radix="16">34 58 </i2c_write> <sleep ms="10"/>
    
    =====CHA_VERTICAL_BACK_PORCH=======
        <i2c_write addr="0x2D" count="1" radix="16">36 17</i2c_write> <sleep ms="10"/>
    
    =====CHA_HORIZONTAL_FRONT_PORCH=======
        <i2c_write addr="0x2D" count="1" radix="16">38 28</i2c_write> <sleep ms="10"/>
    
    =====CHA_VERTICAL_FRONT_PORCH=======
        <i2c_write addr="0x2D" count="1" radix="16">3A 01</i2c_write> <sleep ms="10"/>
    
    =====COLOR BAR =======
        <i2c_write addr="0x2D" count="1" radix="16">3C 18</i2c_write> <sleep ms="100"/>
    
    ======enhanced framing and Vstream enable======
    
      <i2c_write addr="0x2D" count="1" radix="16">5A 0C </i2c_write> <sleep ms="100"/>
    
    ======DUMP CFR======
        <i2c_write addr="0x2D" count="0" radix="16">20</i2c_write> <sleep ms="10"/>
    
    ======Read======
        <i2c_read addr="0x2D" count="32" radix="16">00</i2c_read> <sleep ms="10"/>
    
    
    
    </aardvark>
    

    Regards

  • Hi Sir,

    Also need setting Page 7, right?
    The TEST2 pin must be high at rising edge of EN pin ?

     ======Page 7======

      <i2c_write addr="0x2D" count="1" radix="16">FF 07</i2c_write>
      /> ======ASSR Control to RW from R-only. TEST2 pin must be high at rising edge of EN pin ======
      <i2c_write addr="0x2D" count="1" radix="16">16 01</i2c_write>
     
     The HPD don't need votage, right
     
     /> ======Disable HPD======
      <i2c_write addr="0x2D" count="1" radix="16">5C 01</i2c_write>
     
     
    About 0x5A, it first time is 04 2'nd time is 0C, we follow the sequence is OK?
    ======enhanced framing======
      <i2c_write addr="0x2D" count="1" radix="16">5A 04</i2c_write>
    ======enhanced framing and Vstream enable======
      <i2c_write addr="0x2D" count="1" radix="16">5A 0C</i2c_write>
     
    Are these Read and DUMP must?
     
     ======Read======
      <i2c_read addr="0x2D" count="6" radix="16">00</i2c_read>
      <sleep ms="10" />
    ======Read======
      <i2c_read addr="0x2D" count="1" radix="16">00</i2c_read>
      <sleep ms="10" />
     
     ======DUMP CFR======
      <i2c_write addr="0x2D" count="0" radix="16">20</i2c_write>
      <sleep ms="10" />
      ======Read======
      <i2c_read addr="0x2D" count="32" radix="16">00</i2c_read>
      <sleep ms="10" />
     
     
    Thanks for support.
  • Hello,

    Does the panel support ASSR? If yes, you have to skip Page 7 changes and enable ASSR in your panel.  DSI86 is enabled for ASSR by default because it is intended for eDP panels.  Attached document has an example of how to enable ASSR in a panel.

    8407.DSI86_SW_EXAMPLES.PDF

    Regards