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Display Port lane geometry

Hi,

in the datasheets of most of your display port related ICs you suggest to use the smallest possible trace width and clearance for the 100 ohm differential high speed signals as possible.

Regarding noise immunity I agree that as-closely-as-possible coupled diffpairs should perform best.

But what about the attenuation? In terms of level loss per inch, it should be beneficial to have wider traces, right?

What is the reason for the small-as-possible recommendation? Are there certain limitations to that? Most PCB manufacturers are able to etch traces smaller than 75um (3mil), is that - in any case - what we should aim for?

Thanks for sharing your opinion!
Simon