TDFP401A-Q1 timing specification

Hello,

We are working to get this information and we'll reply soon.

Regards

Hi Elias,

Thank you for your support.
I'm looking forward to your reply.

Could you also please reply to the following post?
e2e.ti.com/.../552123

Best Regards,
Ryuji Asaka

Hi Elias,

Any update on this?

Best Regards,
Ryuji Asaka

Hello Elias,

My original questions are following.
I think that these values are not specified TFP401A too.

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(1) tp(PDH-V) , twL(PDL_MIN)
Please let me know the tp(PDH-V) and twL(PDL_MIN) of the Figure 9, 10 ?
There is no timing requirement.

(2) Delay from /PDO low to high
Please let me know the delay time between /PDO low to high and Data output on the condition of /PD=H.

(3) PLL settling time
Please let me know the delay time between /PD low to high and ODCK output.
There is no ODCK in the figure 9.
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Best Regards,
Ryuji Asaka

Hello,

Thank you.
How about tp(PDH-V)?

Best Regards,
Ryuji Asaka

Hello Elias,

Sorry for bothering you.
Could you please let me know about tp(PDH-V)?
Is this 100ps(typ) ?

Best Regards,
Ryuji Asaka

Hello,

Thank you. I understood the situation.
I'm checking their issue and waiting feedback now.
I will let you know after getting their feedback.

Best Regards,
Ryuji Asaka

Hi Elias,

Regarding tp(PDH-V), the customer accept that there is no data.

On the other hand they measured PLL settling time.
And the result is about 10us.
Is it sufficient to estimate this delay time up to 1 ms?

Best Regards,
Ryuji Asaka