before i shotgun the chip i was wondering what could possibly be keeping the reset line low (spec says if PD is high an internal pull-down will keep reset low) but PD is pulled to GND. this is a proven design in production for 10 years.
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before i shotgun the chip i was wondering what could possibly be keeping the reset line low (spec says if PD is high an internal pull-down will keep reset low) but PD is pulled to GND. this is a proven design in production for 10 years.
It is always low and PD is directly connected to GND through a 0Ω resistor. For reference the specific chip we use is the TSB41BA3A-EP and the thermal pad is not soldered (we are in the process of changing the build instructions to attach the thermal pad).