On the SN65LV1023A side,TCLK was driven by a 12MHz clock from FPGA. On the SN65LV1224B side,REFCLK was driven by a 12MHz clock from the same FPGA. That is,the SERIALIZER and DESERIALIZER was on the same board and controlled by the same FPGA.
Random-Lock Synchronization mode was used.In the loop test, the LOCK signal changed from high to low,and then low to hign.No matter the data stream is changeless(0x01F) or increased.When unlocked,data was lost.
How to solve the problem?
