TFP401: TFP401/401A : Condition of SCDT's Low.

Hello,
DE is decoded from the TMDS stream, if SCDT is low then the TMDS stream is carrying a low in DE, when DE is low the TFP401 will output on QE[]/QO[] the value corresponding to the TMDS signal received, when DE is low the TMDS signal is supposed to carry the blanking information.
You should double check your TMDS source to make sure it is outputting the correct signal.
Does it happens at multiple clock frequencies?
Can you share your schematic?
Regards

Hi,

Because I do not understand a specification of the HDMI, please tell me how DE is decoded.

Which is correct the following?

a.It is created from a timing of HSYNC,VSYNC while blanking.
b.It is created by Packet of Data.
c.Others.

Best Regards,
Shigehiro Tsuda

Hello,
Your graphics processor will set DE=high when it is transmitting the video data and it will set DE=low during the blanking periods, VSYNC, HSYNC and the CTL[] signals will be transmitted during these blanking periods.
The TFP401 will take the TMDS stream and de-serialize it, it will then look on the de-seralized data for transitions on DE, id there are not transitions per the specified time in the datasheet then the TFP401 will "assume" there is no valid data and thus will set SCDT low.

Regards

Hi Elias,

Thank you for quick reply.

There is the additional question.
Is the HSYNC/VSYNC output formed from De-Serialized DATA?
Is it possible under conditions of anything that data output all zero by TFP401A device oneself?

Best Regards,
Shigehiro Tsuda

Hello,
Yes, SYNC signals are decoded from the TMDS stream, the TFP401A won't likely output a all-zero signal by itself, when there is no valid TMDS input the TFP401A will output a free-run clock signal with random data, that is why it is useful to connect SCDT to PDO#

Regards

Hi Elias,

Thank you for quick reply.

I understood your answer.

There is an additional question.
When the abnormality of the timing occurs by noises of the HDMI, how becomes the following signals?
1.HSYNC
2.VSYNC
3.DE
4.data
Which timing will it be to return when a timing returns normally after becoming normal?
a. After 1 vsync
b. After 2 vsync
c.Other than it

Best Regards,
Shigehiro Tsuda

Hi Elias,

Thank you for quick reply.

I understood your answer.

There is an additional question.
When the abnormality of the timing occurs by noises of the HDMI, how becomes the following signals?
1.HSYNC
2.VSYNC
3.DE
4.data

Which timing will it be to return when a timing returns normally after becoming normal?
a.After 1 Vsync
b.After 2 Vsync
c.Other than it

Best Regards,
Shigehiro Tsuda

Hello,
All the above signals will be affected by an invalid TMDS stream.
It will take 1600 tpix from the transition of the first valid DE to the output data.

tpix is the pixel time defined as the period of the RxC clock input

Hi Elias,

Thank you for your quick reply.
I understood it by your detailed explanation.

There is an additional question.
Even if an abnormal signal is input into TFP401 by a noise, there is not the function to stop the input of the data of the TMDS stream, and is it correct by understanding to output the data which have been sent?

Best Regards,
Shigehiro Tsuda

Hello,
Correct.
We recommend to connect SCDT to PDOz, this way, whenever the TMDS signal is not valid SCDT will go low and will turn off the output drivers.
Regards

Hi Elias,

Thank you for quick reply.

There is an additional question.
There are following description in eratta of TFP401.

www.tij.co.jp/.../sllz036.pdf

2. Sync Detect Description
2.1 Changes to document:

TO The TFPX01 offers an output, SCDT, to indicate link activity. The TFPX01 monitors activity on DE to determine if the link is active. When 2^18 clocks produced by an on-chip free running oscillator whose frequency is around 10-15 MHz pass without a transition on DE, the TFPX01 considers the link inactive and SCDT is driven low. Hence SCDT goes low after the terminal count of the counter is reached that is 17~26 ms. When SCDT is low, if 8 DE edges are detected within the terminal count of 2^18 clocks, the link is considered active and SCDT goes high. In the Sync Detect description information on page 14 in the TFP403 datasheet change:

FROM The TFP403 offers an output, SCDT to indicate link activity. The TFP403 monitors activity on DE to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a transition on DE, theTFP403 considers the link inactive and SCDT is driven low. The SCDT goes high immediately after the first transition on DE. The SCDT again becomes low when no more transitions are seen after 2^18 oscillator clocks.

It is not changed even if I refer to a datasheet of TFP401.
Please tell me which is correct.

Best Regards,
Shigehiro Tsuda

Hello,
The Errata is valid, you should take the values in the errata.
Regards

Hi Elias,

Thank you for your quick reply.
I understood that the eratta is correct.

Best Regards,
Shigehiro Tsuda