SN65DP159: "DEV_FUNC_MODE” Register setting

Hi Kawai-san,

HDMI2.0 provides support for data rates between 3.4Gbps and 6Gbps.

Q1). What is the difference between REG 0x0A [1:0]  DEV_FUNC_MODE set to "01(Default)" and "10" ?

        The difference is the crossover point for "01" it is 1Gbps, for "10" it is 3.4Gbps

Q2). Why is the setting "10 : Automatic Retimer for HDMI2.0" prepared for ?

        Using automatic retimer for HDMI2.0 will use redriver for data rates below 3.4Gbps, this will save power in applications where a retimer is not needed.

Q3). For REG 0x0A [1:0] = "10" Automatic retimer for HDMI2.0, what is the criteria for the device to shift between redriver and reclocker ? Is it TMDS clock frequency ? If yes, what is the threshold frequency ?

       The criteria es the TMDS_CLOCK_RATIO_STATUS, if this bit is set the clock period is 40 times TMDS bit period(default is 10 times). tis feature provides support for data rates from 3.4Gbps to 6Gbps.

Q4). Is there any pin or register to know whether the device is operating in Retimer mode or Redriver mode ?#

        Customer can check if the PLL is enabled, is in in page 1, register 0x00, bit 0

       Write 0x01 toregister 0xFF. To select Page 1

       Read register 0x00, bit 0. Check PLL is enabled

       Write 0x00 toregister 0xFF. To select Page 0

      If the customer has EyeScan tool, they can check if they can take eye diagrams, this is only possible in retimer mode.

Regards

Hi Kawai-san,

How do customer know DP159 is in redriver mode?

Q3) HDMI has three data lanes and one clock lane, before HDMI2.0 the data rate of data lanes is ten time the frequency of clock lane.
For HDMI2.0 the data rate of data lanes is forty time the frequency of clock lane, this is to avoid having a very high clock frequencies.

This change of ration between data rate and clock frequency is signaled with TMDS_CLK_RATIO, this comand is sent over DDC and DP159 snoops it to configure itself.
So, this bit is set automatically from snooping DDC or you can set it manually

Q4) if the PLL is inabled the device is in retimer mode, this could be checked in page 1, register 0x00, bit 0

Regards

Hi Kawaisa-san,

You are right, DP159 monitors TMDS_CLK frequency to know if it has to switch from redriver to retimer mode in default mode.

If DDC is not connected, TMDS_CLK_RATIO has to be configured manually, otherwise, DP159 won't know when TMDS_CLK frequency is 1/40 of the data rate.

This will affect the crossover point when switching from redriver to retimer is in HDMI2.0 mode.

Regards