how to adjust the SN65DP159 register to the promote the signal quality to make the image stable?

HI XuYu,

I guess register 0x4D is 0x0D, right?

Have you tried using DP159 in GPIO mode? this is when I2C_EN = LOW
If I2C_EN = HIGH, DP159 will be in I2C mode, but EQ is still adaptive, you need to select fixed EQ in register 0x0A to select an EQ from register 0x0D.
After making EQ changes, assert the bit APPLY_RXTX_CHANGES in register 0x0A.

Do you have an EVM? can you use EyeScan tool on your platform?

Regards

Hi SIR,We have not an EVM and EyeScan tool on your platform.the register 0x4D is the SLLA358 Application Report's register configruation.We have not tried using GPIO mode.Do GPIO mode and I2C mode have different?We is using I2C mode.Do
you have a suitable the edit value of register 0x0A and egister 0x0D ?We have type source code as follow:
void initial_prog_dp159 (void) {
xil_printf ("\r\nInitializing DP159...");
write_csr (0xFF, 0x00); // Select Page 0
write_csr (0x09, 0x36); // Enable X-Mode
write_csr (0x0A, 0x7B); // Disable HPD_SNK pass-thru to HPD_SRC. Enable AUX
// write_csr (0x0D, 0xC0); // Clock on AUX is 1/40 datarate and enabled.
write_csr (0x0D, 0x80); // Clock on AUX is 1/20 datarate and enabled.

write_csr (0x0C, 0x6D); // Set TX Swing to MAX
// write_csr (0x0C, 0x00); // Set TX Swing to NOM
if (en_char_align) {
write_csr (0x10, 0x00); // Turn off pattern verifier
} else {
write_csr (0x10, 0x11); // Len = PRBS23, Sel = PRBS mode to turn off char-alignment !!!!!!!!
}
write_csr (0x16, 0xF1); // Enable DP_TST_EN (disable char-alignment on all lanes)
write_csr (0xFF, 0x01); // Select Page 1
// CONFIGURE PLL BLOCK
write_csr (0x00, 0x02); // Enable Bandgap.
tstate = TSTATE_OFF;
write_csr (0x04, 0x80); // PLL_FBDIV is 40
write_csr (0x05, 0x00); //
write_csr (0x08, 0x00); //
write_csr (0x0D, 0x02); // Selects Lane0 for clock.
write_csr (0x0E, 0x03); // CDR_CONFIG[4:0]. FIXED, LN0.
write_csr (0x01, 0x01); // CP_EN is PLL mode
write_csr (0x02, cpi_cr); // CP_CURRENT
write_csr (0x0B, pll_ctrl_cr); // Test. May not use.
write_csr (0xA1, 0x02); // Oscillator enable.
write_csr (0xA4, 0x02); // Override enables.
// CONFIGURE TX BLOCK
write_csr (0x10, 0xF0); // ENTX Disable
write_csr (0x11, 0x30); // TX_RATE is Full Rate, TX_TERM = 75 to 150 , TX_INVPAIR = None
write_csr (0x14, 0x00); // HDMI_TWPST1 is 0dB de-emphasis
write_csr (0x12, 0x03); // SLEW_CTRL is Normal, SWING is 600mV.
write_csr (0x13, 0xFF); // FIR_UPD. Load TX settings
write_csr (0x13, 0x00); //

// CONFIGURE RX BLOCK
write_csr (0x30, 0xE0); // Disable Receivers
write_csr (0x32, 0x00); // PD_RXINT
write_csr (0x31, 0x00); // RX_RATE is Full
// write_csr (0x4D, 0x28); // EQFTC = 2 and EQLEV = 8
write_csr (0x4D,0x08); // EQFTC = 1 and EQLEV = 2
// write_csr (0x4C, 0x03); // Enable Adaptive EQ
write_csr (0x4C, 0x01); // Enable Fixed EQ (must not use adaptive when RX is disabled)
write_csr (0x34, 0x01); // Enable Offset Correction (gated by rx_ld) !!!!
write_csr (0x3C, 0x04); // Change default of CDR settle
write_csr (0x32, 0xF0); // Load Rx Settings
write_csr (0x32, 0x00); //
write_csr (0x33, 0xF0); // Load EQ settings
// write_csr (0x33, 0x00); // JMS - Just leave EQ_LD on continuously ??????????????
write_csr (0x30, 0xE0); // Enable lane 0 analog only
write_csr (0xFF, 0x00); // Select Page 0
write_csr (0x0A, 0x3B); // Enable HPD_SNK pass thru to HPD_SRC. Retimer.
write_csr (0xFF, 0x01); // Select Page 1
xil_printf ("..done !!\r\n");
}


void tp1_prog_dp159 (XTmrCtr *InstancePtr, u8 link_lanecnt, u16 link_bw) {

// Get time that handler was entered
tp1_start_time.tic = tics;
tp1_start_time.sub = XTmrCtr_GetValue (InstancePtr, TIMER_CNTR_0);

// config_dp159 (TSTATE_TP1); // Note: this routine sets the link_bw and link_lanecnt vars
tstate = TSTATE_TP1;
if (link_bw == LBW_HBR2) tp1_handler_cnt_hbr2++;
if (link_bw == LBW_HBR) tp1_handler_cnt_hbr++;
if (link_bw == LBW_RBR) tp1_handler_cnt_rbr++;
u8 rtxen, eqreg, tsten;
// xil_printf("\r\n link_lanecnt = %d",link_lanecnt);
rtxen = (link_lanecnt == 1) ? 0xE1 : (link_lanecnt == 2) ? 0xC3 : 0x0F;
eqreg = ((link_bw == LBW_HBR2) ? 0x0 : (link_bw == LBW_HBR ) ? 0x1 : 0x2 ) << 4 | (eq_lev & 0x0F);
tsten = (link_lanecnt == 1) ? 0x11 : (link_lanecnt == 2) ? 0x31 : 0xF1; // rval = (((((0x01 << link_lanecnt)-1) & 0xF)<<4) | 0x01);
// 1 : 0x11, 2 : 0x31, 4 : 0xF1
// Add all BW_handler processing here...
write_csr(0x00, 0x02 ); // Enable Bandgap, DISABLE PLL, clear A_LOCK_OVR (to reset it)
write_csr(0x01, 0x01 ); // CP_EN = PLL (reference) mode
write_csr(0x0B, pll_ctrl_cr); // Set PLL control
write_csr(0x02, cpi_cr ); // Set CP_CURRENT
write_csr(0x30, rtxen ); // Enable RX lanes
write_csr(0x00, 0x03 ); // Enable Bandgap, ENABLE PLL, clear A_LOCK_OVR
write_csr(0x4C, 0x01 ); // Enable fixed EQ (to reset adaptive EQ logic)
write_csr(0x4D, 0x08 ); // Set EQFTC and EQLEV (fixed EQ)

// Wait for PLL lock...
lock_cnt = 0;
lock_status = 0;
if (use_lock_cmplt) {
ReadBuffer[0] = 0;
while (ReadBuffer[0] == 0 && lock_cnt < lock_wait) {
read_csr (0x00);
ReadBuffer[0] = ReadBuffer[0] & 0x40; // 0x80;
lock_cnt++;
}
lock_status = (ReadBuffer[0] != 0);
} else {
// Just wait a fixed delay
u32 c1, c2, c3;
c1 = XTmrCtr_GetValue (InstancePtr, TIMER_CNTR_0); // Starting count of timer
c2 = (tp1_fixed_delay * (TIMER_CLK_FREQ/1000000)); // delta count equal to tp1_fixed_delay us
while (c3 = XTmrCtr_GetValue (InstancePtr, TIMER_CNTR_0),
(((c1 - c3) + TIMER_PERIOD) % TIMER_PERIOD) < c2) ;
}

// Get time that DP159 PLL was locked
tp1a_start_time.tic = tics;
tp1a_start_time.sub = XTmrCtr_GetValue (InstancePtr, TIMER_CNTR_0);

u16 cpi, pll_ctrl;
if (link_bw == LBW_HBR2) {
// lock_cnt_hbr2 = lock_cnt;
cpi = cpi_pd_hbr2;
pll_ctrl = pll_ctrl_pd_hbr2;
} else if (link_bw == LBW_HBR ) {
// lock_cnt_hbr = lock_cnt;
cpi = cpi_pd_hbr;
pll_ctrl = pll_ctrl_pd_hbr;
} else {
// lock_cnt_rbr = lock_cnt;
cpi = cpi_pd_rbr;
pll_ctrl = pll_ctrl_pd_rbr;
}
write_csr (0x10, rtxen); // Enable TX lanes
write_csr (0x00, (0x23 | ((exp_res & 0x1)<<2))); // Enable PLL and Bandgap, set A_LOCK_OVR, and set expand LPRES
write_csr (0x02, cpi ); // CP_CURRENT
write_csr (0x0B, pll_ctrl ); // Set PLL control
write_csr (0x01, 0x02 ); // CP_EN is PD mode
write_csr (0xFF, 0x00 ); // Select page 0
if (en_char_align) {
write_csr (0x16, tsten); // Set DP_TST_EN per #lanes, latch FIFO errors
write_csr (0x10, 0x00); // Disable PV (allows char-align and 8b10 decode to operate)
} else {
write_csr (0x16, 0xF1); // Set DP_TST_EN on all lanes to disable char-alignment
write_csr (0x10, 0x11); // Len = PRBS23, Sel = PRBS mode to turn off char-alignment !!!!!!!!
}
write_csr (0xFF, 0x01); // Select page 1
}


void tp2_prog_dp159 (XTmrCtr *InstancePtr, u8 link_lanecnt, u16 link_bw) {
tp23_start_time.tic = tics;
tp23_start_time.sub = XTmrCtr_GetValue (InstancePtr, TIMER_CNTR_0);
if (link_bw == LBW_HBR2) tp23_handler_cnt_hbr2++;
else if (link_bw == LBW_HBR) tp23_handler_cnt_hbr++;
else tp23_handler_cnt_rbr++;
// config_dp159 (TSTATE_TP2);
tstate = TSTATE_TP2;
// tp23_start_training_lane_0_set = dprx_reg_read (XILINX_DISPLAYPORT_RX_DPCD_TRAINING_LANE_0_SET);
// tp23_start_training_lane_1_set = dprx_reg_read (XILINX_DISPLAYPORT_RX_DPCD_TRAINING_LANE_1_SET);
// tp23_start_training_lane_2_set = dprx_reg_read (XILINX_DISPLAYPORT_RX_DPCD_TRAINING_LANE_2_SET);
// tp23_start_training_lane_3_set = dprx_reg_read (XILINX_DISPLAYPORT_RX_DPCD_TRAINING_LANE_3_SET);
write_csr (0x4C, 0x03); // Enable Adaptive EQ
write_csr (0xFF, 0x00); // Select page 0
write_csr (0x15, 0x18); // Clear BERT counters and TST_INTQ latches -- Self-clearing in DP159
// write_csr (0xFF, 0x01); // Select page 1
// write_csr (0xFF, 0x00); // Select page 0
err_cnt = read_csr (0x18); // Read core BERT counter [7:0]
err_cnt += ((read_csr(0x19) & 0xF) << 8); // Read core BERT counter [11:8]
write_csr (0xFF, 0x01); // Select page 1
}

void disconnect_prog_dp159 (void) {
disconnect_cnt++;

// config_dp159 (TSTATE_DIS);
// tstate = TSTATE_DIS;

// if (tstate == TSTATE_RUN) {
write_csr (0x00, 0x02); // Enable Bandgap, disable PLL, clear A_LOCK_OVR
write_csr (0x34, 0x01); // Enable Offset Correction (when RX next enabled) !!!!
write_csr (0x02, cpi_cr); // Set CP_CURRENT
write_csr (0x01, 0x01); // CP_EN = PLL (reference) mode
write_csr (0x0B, pll_ctrl_cr); // Set PLL control
write_csr (0x4D, (0x08); // EQFTC = 1 and EQLEV = 2
write_csr (0x4C, 0x01); // Enable fixed EQ (use fixed when RX disabled)
write_csr (0x33, 0xF0); // Load EQ settings // JMS - make sure EQ load is always set
write_csr (0x10, 0xF0); // Disable TX (all lanes)
write_csr (0x30, 0xE0); // Enable RX Lane 0 analog only
// write_csr (0x33, 0x00); //
// }
}

Best Regards

Hi XuYu,

There was some confusion from my side

For UHD@60Hz, 24bpp, 4:4:4

HDMI requires 5.94Gbps (three lanes)

DP requires 4.46Gbps (four lanes)

I see the application is DP159 as DP retimer.

In x-mode the configuration is done through I2C, there is no GPIO option.

The configuration is done in registers of page 1

Configuration script selects fixed EQ.

When you modify the value in 0x4D(EQFTC, EQLEV), do you run the whole configuration script?

When you modify EQLEV do you update EQ in register 0x33?

Regards

Hi Sir,
At above source code indicate when I modify the value in 0x4D(EQFTC, EQLEV),I have run the whole configuration and Load EQ settings.I have modifyed the value in 0x4D(EQFTC, EQLEV) to max value (0x0F) ,But the the signal quality is not very well,the image we got from SN65DP159 to display is blinking.How I modify above the source code to make make the image stable?Do you have the example source code that you have adjusted completely?Is you send a example of the source code and SLLA359 application note to me or not ?

Regards

Hi XuYu,

Higher EQ is not always better, maybe the application needs lower EQ, do you have eye diagrams to share?
I'll send you by email a script to set EQ per lane.

I would need a TI FAE to request document SLLA359 and provinde business case.

Regards

Hi Moises Garcia,
Thank you very much for your script of setting EQ that is very helpful to me.I have modifyed the EQ lower.I have not eye diagrams to share because my hardware platform device is not perfect. If you have document SLLA359,you send me email.

Best Regards.

Hi Moises Garcia,
When I use the SN65DP159 to receive the PC output the 4K/60Hz resolution video ,and the SN65DP159 work normally while the

DP cable which is less than 2 meters connected to a PC.But when I use the DP cable is more than 2 meters,the PC can not

output the 4K/60Hz resolution video,and we have adjusted the EQ to max value or setted adaptive EQ.How can I resolve long

line transmission for SN65DP159?

Best Regards.

Hi XuYu,

When you use the long cable between PC and DP159, the display is still listed in the PC?

Changing EQ makes a difference with cables shorter than 2m?

I would need eye Diagrams to debug it, do you have a TUSB3410 or AarvarkI2C master adapter to use with EyeScan tool?

Regards

When I use the long cable between PC and DP159, the display is still listed in the PC,but the DP159 recvive the video resolution is 800*600.The EQ makes a difference with cables long than 2m.The video signal is weaken when using long cable.I have not eye Diagrams but I know the video signal is weaken.
Best Regards

Hi XuYu,

We will need more data to continue debugging, if you don't have eye-diagrams, could you send a platform to our lab for testing?

Regards

Hi Moises Garcia,
Maybe I think the hardware of my platform lead to the video signal weaken when the cable is more than 2m.Do you have a sn65dp159 example hardware schematic diagram?If you have a schematic diagram,I hope you to send me a e-mail.Thanks.
Regards

Hello Xuyu Xie,

Are you using the SM65DP159 in redriver or retimer mode at 4K2K60?

Hi XuYu,

There is some tweaking you can do
Try increasing Vod, this is done reducing the resistor in Vsadj, values lower than ~6k may cause compliance failure.
Add de-emphasis, set pin PRE_SEL=LOW, this will add some pre-emphasis to compensate bandwidth limited channel.
You could increae slew rate, SLEW_CTL=HIGH, this setting together with PRE_SEL and Vsadj will improve skew performance.

I will send you the reference scheamtic by email, you can share you scheamtic and layout for review too.

Regards

Yes.We are using the SM65DP159 in redriver or retimer mode at 4K2K60.

Hi Moises Garcia,
I haved sended you a sn65dp159 schematic to your e-mail.We have not setted increasing Vod configuration through the hardware of our platform.In my opinion，I think the method of using the register of sn65dp159 to configure is the same as hardware configuration,is my opinion right? Whether reduces The AC coupled 100nF(From GPU) of the sn65dp159TMDS Inputs is effective to increase signal quality or not?
Regards

Hello Xuyu Xie,

I would expect retimer mode to support longer cable lengths than redriver mode at 6G speeds.   Moises can check your schematic to make sure that the DP159 is configured to enter retimer mode at 6G.

Thanks,

JMMN

Hi XuYu,

This is a DP159 as DP retimer application, follow the application note DP159 as DP retimer, the document I send you is the reference schematic for DP++ to HDMI applications.

I have reviewed the schematic and this are my concerns:
There are no 50 ohms pull-ups to 3.3V between DP159 outputs and AC caps.
DP159 inputs come from a DP connector, AC caps are not needed here, AC caps should be placed on DP source side.

Vsadj resistor is very low, I'm not sure what will be the behavior without the pull-ups on the output, 4.75k choose the right value for your application.

OE meets power-up timing? I'm concerned about the 10k pull-up
on SCL_CTL/SDA_CTL we recommend 2k pull-ups but you can keep 4.7k if this is what your system needs and meets I2C proper levels.
On I2C_EN, use a 65k pull-up to avoid getting the device out of I2C mode.
Use 65k resistors on A0-A1
Tie SCL_SRC/SDA_SRC to GND, if possible add 2k pull-ups on SCL_SNK/SDA_SNK to avoid incoming noise.
To avoid high-frequency noise issues add 4.7pF and a 10pF pair on Vcc and Vdd.

Regards

HI Moises Garcia,
The 50 ohms pull-ups to 3.3V between DP159 outputs and AC caps haved placed to the schematic and PCB,but the result is the same.Is there displayport hardware driver chip to adjust the video signal at the PC Output port?I guess the sn65dp159 has played the greatest effect.Do you haved tested distance of the sn65dp159 transmiting 4k video signal?

Hi XuYu,

We don't provide supported length because it depends on several factors, we provide the EQ levels to match the losses in input channel.

We have seen issues in TMDS181 applications because of DDC channel, since we recommend snoop mode in TMDS181/DP159, this channel is not buffered, which may lead to signal degradation.

What is the maximum cable length you can use with FHD?

Regards

HI Moises Garcia,
The maximum cable length we can use with FHD is 3m,but The maximum cable length of the UHD is 2m.Do you have the measures that improve signal quality by modifying the hardware or increaseing the driver chip between the cables?
Regards

Hi XuYu,

We don't have this measurements, you can see in the datasheet the parameters we support:
For input side, you should consider EQ, Vid, Vic, jitter and skew tolerances
For output side, you can consider Vsadj, jitter and skew ranges.

Could you share your layout?
If the layout has no major concerns, the best way to handle this issue will be to send a platform to continue debugging in our lab.

Regards

Hi XuYu,

Have you tried different brand/quality cables?

Regards

Hi Moises Garcia,
I found a special phenomenon about the sn65dp159 using.When the PC haved setuped win7 system,the GPU is connecting the sn65dp159 through the cable, the sn65dp159 could output the normal 4k/60Hz video signal.But when PC haved setuped windows xp system,the sn65dp159 could output the 4k/60Hz video signal ,but the the 4k/60Hz video signal is blinks,seem the video signal is weaken.And the hardware platform ,pc and GPU is the same between at the win7 system and the windows xp system.Why this happens in different computer operating systems?How do I solve this problem?
Regards

Hi XuYu,

Is this behavior happening in Windows XP without DP159?

Is the driver the same for both platforms? The driver may be configuring DP159 in a different way for different Windows versions.

We need scope captures to conduct a proper debugging.

Consult with GPU vendor about the differences of the driver between Windows 7 and XP.

Regards

Hi Moises Garcia,
This behavior is not happening in Windows XP without DP159.Because we use the same cable to connect the monitor,the video signal output is normal.Our PC's GPU is AMD E8860,but the Windows XP's GPU driver is different with win7 GPU diriver.Whether we need to adjust the value of the sn65dp159 register to solve this problem or modify sn65dp159 hardware?
Regards

Hi XuYu,

If it works fine with Windows 7, the DP159 board should be fine, I suspect the XP driver configures the GPU in a way DP159 needs a different EQ level.

Have you tried different DP sources, cable types?

It is hard to debug without scope captures,   cold you send a board to conduct proper debugging?

Regards

Hi Moises Garcia,
When the DP159 output the blinks video signal with Windows XP,we haved found the dp159's AUX_SRCN and AUX_SRCP pin which output the 270MHz clock is not stable by using the oscilloscope to measure the waveform.We guess that if the AUX_SRC clock is stable ,this problem will be solved.What could we adjust make the clock stable?
Regards

Hi Moises Garcia,
Where is your lab?
Regards

Hi XuYu,

I'm escalating this issue, let's handle it by email.

Regards