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TMDS171: Connection of HPD_SNK for DVI

na na78
Guru 16770 points
Part Number: TMDS171

Hi

We have questions for connection of HPD-SNK.

1.
I see there exists internal pull down resister at HPD_SNK.
However, its value seems to be different between Function Block Diagram and Figure 12.
(130Kohm on the Function Block Diagram, 190Kohm on the Figure 12).

Which is correct?

2.
We are assuming the following connection.

Normally, I think 14pin supplies 5V to sink system as for pin placement of DVI connecor.
However, 5V from the DVI connector does not supply to the sink system in our configuration.
(The sink system has the 5V for HPD terminal by itself)

And the voltage applied to HPD_SNK of TMDS171 can be calculated as

3.3V * (Internal PD) / (Internal PD + 0.1 + 4.7) = 3.18V (If Internal pull down resistor was 130Kohm)


It would satisfy HPD VIH(min) = 2.1V > 3.18V, so I think it's OK.

Do you see any problem in our connection for HPD_SNK?

BestRegards

  • 0
    TI__Mastermind 23815 points
    Hi Na Na,

    The function block diagram has a typo, the right value is 190 ohms

    A DVI compliant system most provide 5V 55mA in DDC+5V(pin 14), this signal si provided to read EDID when the monitor is off.
    The votlage you have in HPD looks fine, by spec:
    HPD(high) should be greater than 2.4V
    HPD(LOW) should be below 0.4V

    I see this is a source application, by default TMDS171 is configured for sink applications having more EQ, if this EQ is too much, you may need to reduce EQ.

    Regards
  • 0 in reply to Moises Garcia
    Guru 16770 points
    Mi Moises

    Thank you for your reply.

    Let me confirm your answer?

    >HPD(high) should be greater than 2.4V
    >HPD(LOW) should be below 0.4V

    What kind of parameter do you mean in the above answer? Vih and Vil of HPD?
    I could not see these specs.

    And we have additional question.

    Is it possible to use TMDS171 as retimer for DVI without DDC interface?
    It means SDA_SRC, SCL_SRC, SDA_SNK, SCL_SNK left open.

    BestRegards
  • 0 in reply to na na78
    TI__Mastermind 23815 points

    Hi Na Na,

    Those values are Voh and Vol of HPD that a display should provide, those values come from DVI specification.

    TMDS171 has Vih and Vil than can handle Voh and Vol from DVI specification.

    If you are not using the DDC block from TMDS171, tie SCL_SRC/SDA_SRC to GDN and place 2k pull-ups to 5V on SCL_SNK/SDA_SNK

    Regards

  • 0 in reply to Moises Garcia
    Guru 16770 points

    Hi Moises

    Thank you for your reply.

    Sorry for additional questions as follows.

    HPD_SNK to HPD_SRC just seem like passing through a buffer.

    If HPD_SNK is low, the device moves into power down mode.  Is it right?

    (I2C_EN/PIN is set as low, so the device operates in pin strap mode)

    And as you said, we don't use DDC block.

    I understood your recommendation of how to terminate SDA_SRC, SCL_SRC, SDA_SNK, SCL_SNK pins.

    On the other hand, are there any impact for if SDA_SRC, SCL_SRC, SDA_SNK, SCL_SNK are left open?

    Could you please tell us predictable influence if any?

    BestRegards

  • 0 in reply to na na78
    TI__Mastermind 23815 points

    Hi Na Na,

    Yes, when HPD_SNK=LOW TMDS171 goes to power down mode, although, this can be disabled by I2C.

    Leaving DDC floated may detect noise and make the device consume more power

    Regards