This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN75DP159: Design guide for trace implementation

Part Number: SN75DP159

Hi,

What is the suggested trace parameters we can support at input (from CPU) and the output (to connector) of SN75DP159 individually?

We would like to know the max # of VIA , max length of trace and impedance we can support from this chip at input and output individault.  Currently the input impedance from CPU is 85ohm.

Thanks!

Antony

  • Hi Antony,

    We don't provide maximum trace length either a maximum number of vias, the differential impedance for DP is 100 ohms.
    The integrity of the signals is affected by losses in the channel, jitter, skew, x-talk, this is why we don't offer a max length parameter.
    DP159 can compensate for 15dB of loss in the channel, it can clean skew and jitter too when in retimer mode.

    If possible don't place vias at all, the vias change the impedance of the channel.
    I recommend reviewing TI High-Speed Interface layout guidelines: www.ti.com/.../spraar7f.pdf

    Regards