We are designing DP130 into a new DP sink card, driving an FPGA.
App note SLLA349 tells us to turn off Link Train mode, and set up the device via I2C. The example code has the DPCD register "LINK_BW_SET" (addr 0x100) set to 5.4GHz.
- Will this work for all rates? Will is still get set automatically by AUX snooping, even though LINK_TRAINING_ENABLE=0? Or are we expected to write the correct value to LINK_BW_SET via I2C in real-time during link training?
Thanks..
Nick
