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Part Number: TMDS181
I am using the TMDS181 in source mode. The HDMI source is implemented in an FPGA and the TMDS181 sits between the FPGA's transceiver outputs and the HDMI connector.
In all HDMI 1.4 resolutions, there are no problems. Everything is working fine. HDMI sinks can correctly receive the video from the HDMI source. Works just fine including at 4K30 resolution. But, in HDMI 2.0 mode, it doesn't work. The HDMI sink cannot receive the signal.
After further investigation, I have found that the TMDS181 appears to be dividing the TMDS clock frequency by 4 in HDMI 2.0 mode. For example, the HDMI source is configured to send a 4K60 signal. The correct TMDS clock frequency in this case is 148.5 MHz, one-fourth of the 597 MHz pixel rate of the 4K60 signal. Use a scope, I can problem the IN_CLK pins of the TMDS181 and see that, indeed, the FPGA is outputting a TMDS clock of 148.5 MHz to the TMDS181. Then, if I probe the OUT_CLK pins of the TMDS181, I see a clock frequency of 37.125 MHz, exactly one-fourth the frequency of the clock at the input of the TMDS181.
Of course, I'm well aware of the TMDS_Clk_Ratio mechanism in HDMI 2.0. And, in fact, yes the HDMI source in the FPGA is setting the TMDS_Clk_Ratio bit of the HDMI sink in the correct SCDC register over the DDC channel. I know that the TMDS181 snoops the TMDS_Clk_Ratio sequence and changes some things inside the TMDS when this bit is set in HDMI 2.0 mode. And, I strongly suspect that whatever the TMDS181 is changing when that TMDS_Clk_Ratio bit is set is messing up the TMDS clock output of the TMD181.
Some further proof of this claim. I went into the HDMI source software driver and commented out the single line of code that causes the DDC controller to set the TMDS_Clk_Ratio bit through the SCDC. Otherwise, the HDMI source thinks it is running in HDMI 2.0 mode. The software does not check to see that the HDMI sink actually has its TMDS_Clk_Ratio bit set. So, the HDMI source is sending a 4K60 image. But, the TMD181 does not see the TMDS_Clk_Ratio bit get set, so it thinks the link is running in HDMI 1.4 mode. I probed the TMDS clock input to the TMDS181 and it is correctly running at 148.5 MHz. And, at the OUT_CLK pins of the TMDS181 is see 148.5 MHz. Thus, as long as the TMDS181 doesn't see the TMDS_Clk_Ratio bit get set by the source, it passes the 148.5 MHz TMDS clock straight through without a problem. But, as soon as I uncomment the line of code that allows the DDC controller to set the sink's TMDS_Clk_Ratio bit, the CLK_OUT of the TMDS181 drops to 37.125 MHz. I've tried this several times and it is completely consistent.
So, the question is, why is the TMDS181 dividing the TMDS clock passing through it by 4 when it sees the TMDS_Clk_Ratio bit get set?
This is a strange behavior, could you check the value of register 0x0B in the failing case?
Could you try setting TMDS_CLK_RATIO bit in your driver and do this configuration manually in TMDS181?
0x0B = 1 // Disable DDC monitoring
0x0B = 1 // Set TMDS clock ration to 1/40 manually.
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In reply to Moises Garcia:
Hi John, Are you implementing lane swap? Regards
No lane swap.
I'm working on trying the tests you suggested.
In reply to John Snow:
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