HD3SS3411: Datasheet Parameters Incomplete

Hello,
Sorry for the delay, I am looking for this information.
Regards

Elias,

Any idea when you expect to have information on this?

Hello Daniel,

The HD3SS3411 was designed to work with different Interface protocols (FPD Link, LVDS, PCIE Gen II, III, XAUI and USB3.1) and the device was tested to comply with these standards.
That being said, current allowed would depend on the protocol you are using. Being a passive switch, the device can support very large current even beyond the limits defined by each spec.
How much current do you need to support? We can check it if you can provide more information about on your implementation.

Regards,
Jorge

Jorge,

I see from the datasheet that the Ron and dRon parameters show test conditions of -8mA (which values hopefully also apply for currents of +8mA as well), which should suffice for the application in mind. I raised the question since the current-flow target for this application has however not yet been completely pinned down (it might be closer to 20mA), and since compared with other TI (and competitive) mutiplexer parts, the datasheet appeared to be missing data such as that that would normally be expected to be present.

At this point in the design, an even more important datasheet issue is the second point raised in my post: "Also, the datasheets do not specify the capacitance of the SEL or OEn pins."

Also: "Additionally, please outline what difference in practice (e.g., performance-wise) would typically be found between the HD3SS3411 and HD3SS3411-Q1 versions." This would be in the context of a high-performance non-automotive application. In other words, might there be some performance advantage in designing in the -Q1 part for a non-automotive application?

Further, the most-critical issue at the moment is confirming that the value for the Tsw parameter is correct as indicated in the datasheets (and is not for example "0.5 us"). (Note that if Tsw is correct as stated in the datasheets, that would apparently make the parts the quickest-switching CMOS multiplexers available anywhere ( an important characteristic in our application).)

Please get back to me ASAP regarding this and the input-capacitance issues. Here are some further questions:

a) The datasheets refer to "Adaptive Tracking", but do not explain it much at all. Please explain further what Adaptive Tracking is, why it was implemented, and how these devices would differ performance-wise compared to parts not employing Adaptive Tracking.

b) Please confirm that the frequency response of the multiplexer signal path extends down to DC.

c) The applications portion of the datasheets recommends that OEn be unasserted (high) at power-on, and be asserted (low) only once power is stable. What is the downside of keeping OEn always low? Would the device be expected to function properly?

d) The device eval board makes access to the RSVD pin available, allowing it to be set high or low. Please explain how the RSVD input affects device functionality. Would it by chance affect the Adaptive Tracking functionality?

e) The datasheets do not indicate whether the multipexer breaks before it makes, or makes before it breaks. Please clarify this, as well as the duration of the overlap time when both signals are enabled, or when neither are enabled.

f) The datasheets' Recommended Operating Conditions show that the signal path common-mode voltage Vcm can be as high as 2.0V, while the differential voltage VdiffPP can be as high as 1.8V. The latter implies that the differential voltage Vdiff can be +/-0.9V, which means that the largest voltage with respect to ground on either of the signals of the signal pair can be (Vcm + (Vdiff/2)) = (2.0V + 0.45V) = 2.45V. Such a voltage would be only 50mV less than the Absolute Maximum Rating for the Differential I/O pin voltage of 2.50V. Does this mean that the differential voltage and the common mode voltage cannot both be at their datasheet maximums simultaneously; or are the datasheets somewhat in error?

g) Please confirm that the device (e.g., with performance as expected per the datasheets) can be expected to properly handle the case of a single single-ended signal replicated at both signals of the signal path pair. In the usual differential-signaling application, something similar to this would be the idle- (no-) signaling condition, e.g. utilized in USB3.1 and elsewhere. Please confirm that the more general situation of a differential signal with Vdiff always being 0V, and with Vcm varying (anywhere between 0V and 2V) in an arbitrary manner and arbitrarily quickly, should be able to be properly supported.